Verification

Simulation and verification of generated HDL code against original model, and FPGA-in-the-loop

When you generate HDL code, you can optionally generate a test bench that verifies your generated HDL code against your Simulink model. For help choosing the type of test bench to generate, see Choose a Test Bench for Generated HDL Code. For how to select and run a test bench, see Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor.

Categories

Verification Basics
View differences between original model and HDL implementation
HDL Test Bench
Generate a test bench that verifies generated HDL code against test vectors from Simulink^®
Cosimulation
HDL cosimulation with Simulink (requires HDL Verifier™)
SystemVerilog DPI Test Bench
Generate DPI test bench code from entire Simulink model (requires HDL Verifier)
FPGA-in-the-Loop
Test design in hardware (requires HDL Verifier)
FPGA Data Capture
Capture signal data from live FPGA (requires HDL Verifier)