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Verification

Simulation and verification of generated HDL code against original model, and FPGA-in-the-loop

When you generate HDL code, you can optionally generate a test bench that verifies your generated HDL code against your Simulink model. For help choosing the type of test bench to generate, see Choose a Test Bench for Generated HDL Code. For how to select and run a test bench, see Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor.