You can use a DPI component generated from a Simulink subsystem in two ways :
Export SystemVerilog DPI Component — You can integrate this component into your HDL simulation as a behavioral model. The component generator supports test points and tunable parameters. You can also generate a SystemVerilog test bench that verifies the generated DPI component against data vectors from your subsystem. See Generate SystemVerilog DPI Component.
Generate SystemVerilog DPI Test Bench (with HDL Coder™) — Use this test bench to verify your generated HDL code using C code generated from your entire Simulink model, including the DUT and data sources. See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).
See DPI Component Generation with Simulink. You must have a Simulink Coder™ license to use this feature.
|HDL Verifier||Generate SystemVerilog DPI component from a Simulink subsystem|
|Assertion||Generate SystemVerilog assertions from Simulink assertion|
If you have a Simulink Coder license, you can generate SystemVerilog DPI components using one of two methods.
Choose between the two types of SVDPI test benches.
How to generate a SystemVerilog DPI component. This topic takes you through the workflow of generating a DPI component from Simulink, and explores various configuration parameters.
How to export the generated DPI component to a SystemVerilog environment.
Start ModelSim® or Questa® in GUI mode.
Generate SystemVerilog assertions from your Simulink environment.
Generate a DPI component for an operating system different from your MATLAB® host machine.
Describes how to customize the generated SystemVerilog code.
Generate a DPI component that provides tunable access to a parameter.
You can designate internal signals in your model as test points and configure the SystemVerilog DPI generator to create one or more access functions.
Generate SystemVerilog immediate assertions from
statements and model verification blocks, and collect functional coverage
information (requires Simulink
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.