SystemVerilog DPI Testbenches

HDL Verifier™ provides two types of testbenches that generate a C-language component and integrate it into a SystemVerilog testbench with a direct programming interface (DPI). One testbench verifies a generated C component against saved data vectors from your Simulink^® subsystem. The other testbench verifies generated HDL code against a C component generated from the entire Simulink model.

Component Testbench — When you generate a C component from a Simulink subsystem for use as a DPI component, you can optionally generate a SystemVerilog testbench. The testbench verifies the generated DPI component against data vectors from your Simulink model. This feature is available in the Model Configuration Parameters dialog box, under Code Generation. See Generate SystemVerilog DPI Component.
HDL Code Testbench — When you generate HDL code from a subsystem, using HDL Coder™, you can optionally generate a SystemVerilog testbench. This testbench compares the output of the HDL implementation against the results of the Simulink model. You can access this feature in HDL Workflow Advisor under HDL Code Generation > Set Testbench Options, or in the Model Configuration Parameters dialog box, under HDL Code Generation > Test Bench. Alternatively, for command-line access, set the GenerateSVDPITestBench property of makehdltb (HDL Coder). See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).

Both types of testbenches require a Simulink Coder™ license and the ASIC Testbench for HDL Verifier add-on.

Limitations

HDL Verifier converts matrices and vectors to one-dimensional arrays in SystemVerilog. For example, a 4-by-2 matrix in Simulink is converted to a one-dimensional array of eight elements in SystemVerilog.
These subsystems do not support DPI testbench generation:
- Triggered subsystem
- Enabled subsystem
- Subsystem with action port

Component Testbench

The SystemVerilog DPI component generator also creates a testbench. You can use this testbench to verify that the generated SystemVerilog component is functionally equivalent to the original Simulink subsystem. The testbench saves data vectors from your Simulink simulation to apply as stimuli and to check against the output of the component. This testbench is not intended as a replacement for a system testbench for your own application. However, you can use the generated testbench as a starting example for your own system testbench.

If you enable logging on test points in your model, the generated testbench also compares their signal values in the SystemVerilog component with logged values from Simulink.

Note

HDL Verifier does not support testbench generation for custom generated SystemVerilog code. See Customization.

Multirate Component Testbench

When your subsystem contains signals with more than one sample rate, the generated testbench includes a timing controller module. The timing controller generates input clock signals at the appropriate rates. Input stimuli and expected data outputs are applied and checked according to their sample rates.

HDL Code Testbench

When you generate HDL code from a subsystem, using HDL Coder, you can also generate a SystemVerilog DPI testbench. This testbench compares the output of the HDL implementation against the results of the Simulink model. In addition to C code for your DUT subsystem, the coder also generates C code for the portion of your model that generates the input stimuli. Generation of this testbench is faster than the default HDL testbench for large data sets. This advantage is because the coder does not run the Simulink model to obtain the input and output data vectors. The generated C component calculates input stimuli and the output results for comparison with the HDL implementation.

The generated SystemVerilog testbench includes:

Generated Verilog^® or VHDL^® code for your subsystem
Generated C component
Code to compare the output of the HDL code with the output of the C component.

Run this testbench to verify the generated HDL code implements the same algorithm as your Simulink model.