Enable

Add enable port to subsystem or model

• 

Libraries:
Simulink / Ports & Subsystems
HDL Coder / Ports & Subsystems

Description

The Enable block allows an external signal to control execution of a subsystem or a model. To enable this functionality, add the block to a Subsystem block or at the root level of a model that is referenced by a Model block.

If you use an enable port at the root-level of a model:

• For multi-rate models, set the solver to single-tasking.

• For models with a fixed-step size, at least one block in the model must run at the specified fixed-step size rate.

Examples

Implement Control Algorithm Using Enabled Subsystem

Use an enabled subsystems to implement a control algorithm based on a binary logic signal. The enabled subsystems execute when the binary signal has a positive value and implements the control algorithm. In this example, the super-twisting control algorithm is used to stabilize an unstable dynamic system. The super-twisting algorithm is one of the well known sliding mode control techniques for its robust performance.

• Open Live Script

Control Block States and Output of Enabled Subsystem

Reset or hold states of blocks inside an Enabled Subsystem block when the subsystem is disabled and how to control the subsystem output. In this example, you see four different combinations of state and output value configurations for both discrete and continuous control signals. When the enabled subsystem is disabled, the combinations work as follows:

• Open Model

Illustration of Law of Large Numbers

Use MATLAB System blocks to illustrate the law of large numbers.

• Open Model

Counters Using Conditionally Executed Subsystems

Implement counters using Enabled and Triggered subsystems. In this example, the model sldemo_counters controls flow of water into a tank and uses a counter to count the number of times overflow occurs, where overflow occurs when the water level in the tank is 8 meters or more for 30 seconds or more.

• Open Live Script

Building a Clutch Lock-Up Model

Use Simulink® to model and simulate a rotating clutch system. Although modeling a clutch system is difficult because of topological changes in the system dynamics during lockup, this example shows how enabled subsystem can easily handle such problems. We illustrate how to employ important Simulink modeling concepts in the creation of the clutch simulation. Designers can apply these concepts to many models with strong discontinuities and constraints that may change dynamically.

• Open Model

Ports

Output

Enable signal — External enable signal for a subsystem or model

scalar

Enable signal attached externally to the outside of an Enabled Subsystem block and passed to the inside of the subsystem. An enable signal port is added to an Enable block when you select the Show output port parameter.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | expression

Parameters

States when enabling — Select block states when subsystem or model is disabled

held (default) | reset

When a Subsystem block or Model block is disabled, select what happens to block states for the blocks within the subsystem or model.

held

Hold block states at their previous values.

reset

Reset block states to their initial conditions (zero if not defined).

Programmatic Use

Block parameter: StatesWhenEnabling

Type: character vector

Values: 'held' | 'reset'

Default: 'held'

Propagate sizes of variable-size signals — Select when to propagate a variable-size signal

Only when enabling (default) | During execution

Select when to propagate a variable-size signal.

Only when enabling

Propagate a variable-size signal when reenabling a Subsystem block or Model block containing an Enable port block. When you select this option, sample time must be periodic.

During execution

Propagate variable-size signals at each time step.

Programmatic Use

Block parameter: PropagateVarSize

Type: character vector

Values: 'Only when enabling' | 'During execution'

Default: 'Only when enabling'

Show output port — Control display of output port for enable signal

off (default) | on

The output port passes the enable signal attached externally to the outside of an Enabled Subsystem block or enabled Model block to the inside.

off

Remove the output port on the Enable port block.

on

Display an output port on the Enable port block. Selecting this option allows the subsystem or model to process the enable signal.

Programmatic Use

Block parameter: ShowOutputPort

Type: character vector

Values: 'off' | 'on'

Default: 'off'

Enable zero-crossing detection — Control zero-crossing detection

on (default) | off

Control zero-crossing detection for a model.

on

Detect zero crossings.

off

Do not detect zero crossings.

Programmatic Use

Block parameter: ZeroCross

Type: character vector

Values: 'on' | 'off'

Default: 'on'

Port dimensions — Specify dimensions for the enable signal

1 (default) | [n] | [m n]

Specify dimensions for the enable signal attached externally to a Model block and passed to the inside of the block.

1

Scalar signal.

[n]

Vector signal of width n.

[m n]

Matrix signal having m rows and n columns.

Programmatic Use

Block parameter: PortDimensions

Type: character vector

Values: '1' | '[n]' | '[m n]'

Default: '1'

Sample time — Specify time interval

-1 (default) | Ts | [Ts, To]

Specify time interval between block method execution. See Specify Sample Time.

-1

Sample time inherited from the model.

Ts

Scalar where Ts is the time interval.

[Ts, To]

Vector where Ts is the time interval and To is the initial time offset.

Programmatic Use

Block parameter: SampleTime

Type: character vector

Values: '-1' | 'Ts' | '[Ts, To]'

Default: '-1'

Minimum — Specify minimum output value for the enable signal

[] (default) | real scalar

Specify minimum value for the enable signal attached externally to a Model block and passed to the inside of the block.

Simulink^® uses this value to perform:

• Simulation range checking. See Specify Signal Ranges.

• Automatic scaling of fixed-point data types.

• Optimization of generated code. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. See Optimize using the specified minimum and maximum values (Embedded Coder).

[]

Unspecified minimum value.

real scalar

Real double scalar value.

Programmatic Use

Block parameter: OutMin

Type: character vector

Values: '[]' | real scalar in quotes

Default: '[]'

Maximum — Specify maximum output value for the enable signal

[] (default) | real scalar

Specify maximum value for the enable signal attached externally to a Model block and passed to the inside of the block.

Simulink uses this value to perform:

• Simulation range checking. See Specify Signal Ranges.

• Automatic scaling of fixed-point data types.

• Optimization of generated code. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. See Optimize using the specified minimum and maximum values (Embedded Coder).

[]

Unspecified maximum value.

real scalar

Real double scalar value.

Programmatic Use

Block parameter: OutMax

Type: character vector

Values: '[]' | real scalar in quotes

Default: '[]'

Data type — Specify output data type for the enable signal

double (default) | single | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | boolean | fixdt(1,16) | fixdt(1,16,0) | fixdt(1,16,2^,0) | <data type expression>

Specify data type for the enable signal attached externally to a Model block and passed to the inside of the block.

double

Double-precision floating point.

single

Single-precision floating point.

int8

Signed 8-bit integer.

uint8

Unsigned 8-bit integer.

int16

Signed 16-bit integer.

uint16

Unsigned 16-bit integer.

int32

Signed 32-bit integer.

uint32

Unsigned 32-bit integer.

int64

Signed 64-bit integer.

uint64

Unsigned 64-bit integer.

boolean

Boolean with a value of true or false.

fixdt(1,16)

Signed 16-bit fixed point number with binary point undefined.

fixdt(1,16,0)

Signed 16-bit fixed point number with binary point set to zero.

fixdt(1,16,2^,0)

Signed 16-bit fixed point number with slope set to 2^0 and bias set to 0.

<data type expression>

Data type object, for example Simulink.NumericType. You cannot enter the name of a Simulink.Bus object as a data type expression.

Programmatic Use

Block parameter: OutDataTypeStr

Type: character vector

Values: 'double' | 'single' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'boolean' | '<fixdt(1,16)' | 'fixdt(1,16,0)' | 'fixdt(1,16,2^0,0)' | '<data type expression>'

Default: 'double'

Mode — Select data type category

Built in (default) | Fixed point | Expression

Select data type category and display drop-down lists to help you define the data type.

Built in

Display drop-down lists for data type and Data type override.

Fixed point

Display drop-down lists for Signedness, Scaling, and Data type override.

Expression

Display box for entering an expression.

Dependency

To enable this parameter, select the Show data type assistant button.

Programmatic Use

No equivalent command-line parameter.

Interpolate data — Specify value of missing workspace data

on (default) | off

Specify value of missing workspace data when loading data from the workspace.

on

Linearly Interpolate output at time steps for which no corresponding workspace data exists.

off

Do not interpolate output at time steps. The current output equals the output at the most recent time step for which data exists.

Programmatic Use

Block parameter: Interpolate

Type: character vector

Values: 'on' | 'off'

Default: 'on'

Block Characteristics

Data Types	Boolean | double | fixed point | integer | single
Direct Feedthrough	no
Multidimensional Signals	yes
Variable-Size Signals	no
Zero-Crossing Detection	yes

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

For more information, see HDL Code Generation in Enabled Subsystem.

HDL Architecture

This block has one default HDL architecture.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a