hdl.RAM

Single, simple dual, or dual-port RAM for memory read/write access

Description

hdl.RAM reads from and writes to memory locations for a single, simple dual, or dual-port RAM. The output data is delayed one step. If your input data is scalar, the address and write enable inputs must be scalar, andHDL Coder™ infers a single RAM block. If your data is a vector, HDL Coder infers an array of parallel RAM banks. With vector data input, the address and write enable inputs can be both scalars or vectors. When you specify scalar inputs for the write enable and address ports, the system object applies the same operation to each RAM bank.

The hdl.RAM System object™ can have 231 bytes of internal storage. The RAM size takes into account the address width, the number of bytes that are used to store each word, and the number of RAM banks.

To read from or write to memory locations in the RAM:

1. Create the hdl.RAM object and set its properties.

2. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?.

Creation

Syntax

ram = hdl.RAM

ram = hdl.RAM(Name,Value)

Description

ram = hdl.RAM returns a single port RAM System object that you can write to or read from a memory location.

ram = hdl.RAM(Name,Value) returns a single, simple dual, or dual port RAM System object with properties set using one or more name-value pairs. Enclose each property name in single quotes.

Properties

Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

RAMType — Type of RAM

'Single port' (default) | 'Simple dual port' | 'Dual port'

Type of RAM, specified as either:

• 'Single port' — Create a single port RAM with Write data, Address, and Write enable as inputs and Read data as the output.

• 'Simple dual port' — Create a simple dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address as the output.

• 'Dual port' — Create a dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address and write address as the outputs.

WriteOutputValue — Behavior for Write output

'New data' (default) | 'Old data'

Behavior for Write output, specified as either:

• 'New data' — Send out new data at the address to the output.

• Old data' — Send out old data at the address to the output.

Dependencies

Specify this property when you set RamType to 'Single port' or 'Dual port'. This property does not apply for Simple Dual Port RAM object.

RAMInitialValue — Initial output of RAM

'0.0' (default) | Scalar | Vector

Initial simulation output of the System object, specified as either:

• A scalar value.

• A vector with one-to-one mapping between the initial value and the RAM words.

Usage

Syntax

dataOut = ram(wrData,rwAddress,wrEn)

rdDataOut = ram(wrData,wrAddress,wrEn,rdAddress)

[wrDataOut,rdDataOut] = ram(wrData,wrAddress,wrEn,rdAddress)

Description

dataOut = ram(wrData,rwAddress,wrEn) reads the value in memory location rwAddress when wrEn is false. When wrEn is true, you write the value wrData into the memory location rwAddress. dataOut is the new or old data at rwAddress. Use this syntax when you create a single port RAM System object.

rdDataOut = ram(wrData,wrAddress,wrEn,rdAddress) writes the value wrData into memory location wrAddress when wrEn is true. rdDataOut is the old data at the address location rdAddress. Use this syntax when you create a simple dual port RAM System object.

[wrDataOut,rdDataOut] = ram(wrData,wrAddress,wrEn,rdAddress) writes the value wrData into the memory location wrAddress when wrEn is true. wrDataOut is the new or old data at memory location wrAddress. rdDataOut is the old data at the address location rdAddress. Use this syntax when you create a dual port RAM System object.

Input Arguments

wrData — Write data

Scalar (default) | Vector

Data that you write into the RAM memory location when wrEn is true. This value can be double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data Types: single | double | int8 | int16 | uint8 | uint16 | fi

rwAddress — Write or Read address

Scalar (default) | Vector

Address that you write the wrData into when wrEn is true. The System object reads the value in memory location rwAddress when wrEn is false. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long. Specify this address when you create a single port RAM object.

Data Types: uint8 | uint16 | fi

wrEn — Write enable

Scalar (default) | Vector

When wrEn is true, you write the wrData into the RAM memory location. If you create a single port RAM, the System object reads the value in the memory location when wrEn is false. This value must be logical.

Data Types: logical

rdAddress — Read address

Scalar (default) | Vector

Address that you read the data from when you create a simple dual port RAM or dual port RAM System object. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Data Types: uint8 | uint16 | fi

wrAddress — Write address

Scalar (default) | Vector

Address that you write the data into when you create a simple dual port RAM or dual port RAM System object. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Data Types: uint8 | uint16 | fi

Output Arguments

dataOut — Output data

Scalar (default) | Vector

Output data that the System object reads from the memory location rwAddress a single port RAM object when wrEn is false.

rdDataOut — Data from Read address

Scalar (default) | Vector

Old output data that the System object reads from the memory location rdAddress of a simple dual port RAM or dual port RAM System object.

wrDataOut — Data from Write address

Scalar (default) | Vector

New or old output data that the System object reads from the memory location wrAddress of a simple dual port RAM or dual port RAM System object.

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

Common to All System Objects

step	Run System object algorithm
release	Release resources and allow changes to System object property values and input characteristics
reset	Reset internal states of System object

Examples

Observe Previous Data at Write Time

Construct System object to read from or write to a memory location in RAM. Set WriteOutputValue to Old data to return the previous value stored at the write address.

The output data port corresponds to the read/write address passed in. During a write operation, the old data at the write address is sent out as the output.

Note: This object syntax runs only in R2016b or later. If you are using an earlier release, replace each call of an object with the equivalent step syntax. For example, replace myObject(x) with step(myObject,x).

ram_1p = hdl.RAM('RAMType','Single port',...
                           'WriteOutputValue','Old data')

ram_1p = 
  hdl.RAM with properties:

             RAMType: 'Single port'
    WriteOutputValue: 'Old data'
     RAMInitialValue: 0

dataLength    = 10;
dataIn = 1:10;
dataOut = zeros(1,dataLength);

Write a count pattern to the memory. Previous values on the first writes are all zero.

for ii = 1:dataLength
  addressIn   = uint8(ii-1);
  writeEnable = true;
  dataOut(ii) = ram_1p(dataIn(ii),addressIn,writeEnable);
end
dataOut

dataOut = 1×10

     0     0     0     0     0     0     0     0     0     0

Read the data back.

for ii = 1:dataLength
  addressIn   = uint8(ii-1);
  writeEnable = false;
  dataOut(ii) = ram_1p(dataIn(ii),addressIn,writeEnable);
end
dataOut

dataOut = 1×10

     0     1     2     3     4     5     6     7     8     9

Now, write the count in reverse order. The previous values are the original count.

for ii = 1:dataLength
  addressIn   = uint8(ii-1);
  writeEnable = true;
  dataOut(ii) = ram_1p(dataIn(dataLength-ii+1),addressIn,writeEnable);
end
dataOut

dataOut = 1×10

    10     1     2     3     4     5     6     7     8     9

Read/Write Single-Port RAM

Create System object that writes to a single port RAM and reads the newly written value.

Note: This object syntax runs only in R2016b or later. If you are using an earlier release, replace each call of an object with the equivalent step syntax. For example, replace myObject(x) with step(myObject,x).

Construct single-port RAM System object. When you write a location, the object returns the new value. The size of the RAM is inferred from the bitwidth of the address and write data on the first call to the object.

ram_1p = hdl.RAM('RAMType','Single port','WriteOutputValue','New data');
dataLength       = 16;
[dataIn,dataOut] = deal(uint8(zeros(1,dataLength)));

Write randomly generated data to the System object, and then read data back out again.

for ii = 1:dataLength
  dataIn(ii)  = randi([0 63],1,1,'uint8');
  addressIn   = fi((ii-1),0,4,0);
  writeEnable = true;
  dataOut(ii) = ram_1p(dataIn(ii),addressIn,writeEnable);
end  
dataOut

dataOut = 1x16 uint8 row vector

    0   52   57    8   58   40    6   17   35   61   61   10   62   61   31   51

for ii = 1:dataLength
  addressIn   = fi((ii-1),0,4,0);
  writeEnable = false;
  dataOut(ii) = ram_1p(dataIn(ii),addressIn,writeEnable);
end
dataOut

dataOut = 1x16 uint8 row vector

    9   52   57    8   58   40    6   17   35   61   61   10   62   61   31   51

Create Simple Dual-Port RAM System Object

Construct System object to read from and write to different memory locations in RAM.

The output data port corresponds to the read address. If a read operation is performed at the same address as the write operation, old data at that address is read out as the output. The size of the RAM is inferred from the bitwidth of the address and write data on the first call to the object.

Note: This object syntax runs only in R2016b or later. If you are using an earlier release, replace each call of an object with the equivalent step syntax. For example, replace myObject(x) with step(myObject,x).

ram_2p = hdl.RAM('RAMType','Simple dual port');
dataLength       = 16;
[dataIn,dataOut] = deal(uint8(zeros(1,dataLength)));

Write randomly generated data to the System object, and read the old data from the same address.

for ii = 1:dataLength
  dataIn(ii)  = randi([0 63],1,1,'uint8');
  wrAddr  = fi((ii-1),0,4,0);
  writeEnable = true;
  dataOut(ii) = ram_2p(dataIn(ii),wrAddr,writeEnable,wrAddr);
end  
dataOut

dataOut = 1x16 uint8 row vector

   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0

Write and read from different addresses. The object returns the read result after one cycle delay.

for ii = 1:dataLength
  wrAddr   = fi((ii-1),0,4,0);
  rdAddr   = fi(dataLength-ii+1,0,4,0);
  writeEnable = true;
  dataOut(ii) = ram_2p(dataIn(ii),wrAddr,writeEnable,rdAddr);
end
dataOut

dataOut = 1x16 uint8 row vector

    0    9    9   51   31   61   62   10   61   61   35   17    6   40   58    8

Create Dual-Port RAM System Object

Construct System object to read from and write to different memory locations in RAM.

There are two output ports: a write output data port and a read output data port. The write output data port sends out the new data at the write address. The read output data port sends out the old data at the read address. The size of the RAM is inferred from the bitwidth of the address and write data on the first call to the object.

Note: This object syntax runs only in R2016b or later. If you are using an earlier release, replace each call of an object with the equivalent step syntax. For example, replace myObject(x) with step(myObject,x).

ram_2p = hdl.RAM('RAMType','Dual port','WriteOutputValue','New data');
dataLength       = 16;
[dataIn,wrDataOut,rdDataOut] = deal(uint8(zeros(1,dataLength)));

Write randomly generated data to the System object, and read the old data from the same address.

for ii = 1:dataLength
  dataIn(ii)  = randi([0 63],1,1,'uint8');
  wrAddr  = fi((ii-1),0,4,0);
  writeEnable = true;
  [wrDataOut(ii),rdDataOut(ii)] = ram_2p(dataIn(ii),wrAddr,writeEnable,wrAddr);
end  
wrDataOut

wrDataOut = 1x16 uint8 row vector

    0   52   57    8   58   40    6   17   35   61   61   10   62   61   31   51

rdDataOut

rdDataOut = 1x16 uint8 row vector

   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0

Write and read from different addresses. The object returns the read result after one cycle delay.

for ii = 1:dataLength
  wrAddr   = fi((ii-1),0,4,0);
  rdAddr   = fi(dataLength-ii+1,0,4,0);
  writeEnable = true;
  [wrDataOut(ii),rdDataOut(ii)] = ram_2p(dataIn(ii),wrAddr,writeEnable,rdAddr);
end
wrDataOut

wrDataOut = 1x16 uint8 row vector

    9   52   57    8   58   40    6   17   35   61   61   10   62   61   31   51

rdDataOut

rdDataOut = 1x16 uint8 row vector

    0    9    9   51   31   61   62   10   61   61   35   17    6   40   58    8

Create Dual-Port RAM with Multiple Banks

Create a System object that can write vector data to a dual-port RAM and read vector data out. Each element of the vector corresponds to a separate bank of RAM. This example creates 4 16-bit banks. Each bank has eight entries.

Note: This object syntax runs only in R2016b or later. If you are using an earlier release, replace each call of an object with the equivalent step syntax. For example, replace myObject(x) with step(myObject,x).

Construct dual-port RAM System object.

ram_2p = hdl.RAM('RAMType','Dual port','WriteOutputValue','New data');

Create vector write data and addresses. Use a 3-bit address (for 8 locations), and write 16-bit data. Read and write addresses are independent. Allocate memory for the output data.

ramDataIn = fi(randi((2^16)-1,1,4),0,16,0);
ramReadAddr = fi([1,1,1,1],0,3,0);
ramWriteAddr = fi([1,1,1,1],0,3,0);
[wrOut,rdOut] = deal(fi(zeros(1,4),0,16,0));

First, write locations in bank 1 and 4, then read all banks. The write data is echoed in the wrOut output argument. The object returns read results after one cycle delay.

[wrOut,rdOut] = ram_2p(ramDataIn,ramWriteAddr,[true,false,false,true],ramReadAddr);
[wrOut,rdOut] = ram_2p(ramDataIn,ramWriteAddr,[false,false,false,false],ramReadAddr);
[wrOut,rdOut] = ram_2p(ramDataIn,ramWriteAddr,[false,false,false,false],ramReadAddr)

wrOut=1×4 object
       53393           0           0       59859

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 16
        FractionLength: 0

rdOut=1×4 object
       53393           0           0       59859

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 16
        FractionLength: 0

Algorithms

In your Simulink^® model, you can use the hdl.RAM inside a MATLAB System or a MATLAB Function block. If you log the output of a MATLAB System block, the output data has at least three dimensions because the MATLAB System block has at least two dimensions, and the time data adds a third dimension. For example, if you input scalar data to the block, the logged output data has the dimension 1x1xN, where N is the number of time steps. To obtain an output dimension that is same as the input dimension, add a Reshape block at the output with Output dimensionality set to Derive from reference input port.

RAM Inference with Scalar Data

If your data is scalar, the RAM size, or number of locations, is inferred from the data type of the address variable.

Data type of address variable	RAM address size (bits)
single or double	16
uintN	N
embedded.fi	WordLength

The maximum RAM address size is 32 bits.

RAM Inference with Vector Data

If your data is a vector, HDL Coder generates an array of parallel RAM banks. The number of elements in the vector determines the number of RAM banks. The size of each RAM bank is inferred from the data type of the address variable.

Data type of address variable	RAM address size (bits)
single or double	16
uintN	N
embedded.fi	WordLength

The maximum RAM bank address size is 32 bits.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.