Single Port RAM System

Single Port RAM block based on hdl.RAM system object with ability to provide initial value

• Library:

• HDL Coder / HDL RAMs

• 

Description

The blocks are MATLAB System blocks that use the hdl.RAM System object™. You can specify the RAM type as Dual port, Simple dual port, or Single port. In terms of simulation behavior, the Single Port RAM System block behaves similar to the Single Port RAM.

By using the MATLAB System block implementation, you can:

• Specify an initial value for the RAM. In the Block Parameters dialog box, enter a value for Specify the RAM initial value.

• Obtain faster simulation results when you use these blocks in your Simulink^® model.

• Create parallel RAM banks when you use vector data by leveraging the hdl.RAM System object functionality.

• Obtain higher performance and support for large data memories.

Limitations

• The block does not support boolean inputs. Cast any boolean types to ufix1 for input to the block.

• When you build the FPGA bitstream for the RAM, the global reset logic does not reset the RAM contents. To reset the RAM, make sure that you implement the reset logic.

• The RAM address can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Ports

Input

din — Write data input

Scalar (default) | Vector

Data that you write into the RAM memory location when wrEn is true. This value can be double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data Types: single | double | int8 | int16 | uint8 | uint16 | fixed point

addr — Write or Read address

Scalar (default) | Vector

Address that you write the data into when wrEn is true. The RAM reads the value in memory location addr when wrEn is false. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Dependencies

To enable this port, set the Specify the type of RAM parameter to Single port.

Data Types: uint8 | uint16 | fixed point

wr_en — Write enable

Scalar (default) | Vector

When wrEn is true, the RAM writes the data into the memory location that you specify. If you set the Specify the type of RAM to Single port, the RAM reads the value in the memory location addr when wrEn is false.

Data Types: Boolean

Output

dout — Output data

Scalar (default) | Vector

Output data that the RAM reads from the memory location addr when wrEn is false.

Dependencies

To enable this port, set the Specify the type of RAM parameter to Single port.

Parameters

Specify the type of RAM — RAM type

Dual port (default) | Simple dual port | Single port

Type of RAM, specified as either:

• Single port — Create a single port RAM with Write data, Address, and Write enable as inputs and Read data as the output.

• Simple dual port — Create a simple dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address as the output.

• Dual port — Create a dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address and write address as the outputs.

The code generator dynamically configures the input and output ports of the block based on the RAM type that you specify.

Specify the output data for a write operation — Write output behavior

New data (default) | Old data

Behavior for Write output, specified as either:

• 'New data' — Send out new data at the address to the output.

• Old data' — Send out old data at the address to the output.

Specify the RAM initial value — Initial simulation output of RAM

'0.0' (default) | Scalar | Vector

Initial simulation output of the System object, specified as either:

• A scalar value.

• A vector with one-to-one mapping between the initial value and the RAM words.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

The block has a MATLABSystem architecture which indicates that the block implementation uses the hdl.RAM System object.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline.
RAMDirective	Specify whether to map RAM blocks in your design to RAM blocks on the target FPGA. For UltraRAM mapping, Specify the RAM initial value must be set to 0. See also RAMDirective.

Complex Data Support

This block supports code generation for complex signals.