HDL Verifier

Test and verify Verilog and VHDL using HDL simulators and FPGA boards

HDL Verifier™ lets you test and verify Verilog^® and VHDL^® designs for FPGAs, ASICs, and SoCs. You can verify RTL with test benches running in MATLAB^® or Simulink^® using cosimulation with HDL simulators. These same test benches can be used with FPGA and SoC development boards to verify HDL implementations in hardware.

HDL Verifier generates SystemVerilog verification models for use in RTL test benches, including Universal Verification Methodology (UVM) test benches. These models run natively in simulators from Siemens^®, Cadence^®, Synopsys^®, and Xilinx^® via the SystemVerilog Direct Programming Interface (DPI).

HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx, Intel^®, and Microchip boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.

What Is HDL Verifier?

HDL Cosimulation

Verify HDL code using MATLAB or Simulink as a testbench. Incorporate legacy HDL into system simulations through cosimulation with HDL simulators including ModelSim and Questa from Siemens EDA, Cadence Xcelium, and the Xilinx Vivado simulator.

Documentation | Examples

UVM Environment Generation

Generate complete Universal Verification Methodology (UVM) test benches from Simulink models. Generate UVM sequences, scoreboards, and predictors and incorporate them into production test benches.

Documentation | Examples

Generate SystemVerilog

Generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems for use in functional verification environments including Synopsys VCS^®, Cadence Xcelium, and ModelSim^® or Questa^® from Siemens EDA.

MATLAB: Documentation | Examples

Simulink: Documentation | Examples

FPGA-in-the-Loop

Use MATLAB or Simulink test benches to test HDL implementations executing on FPGA boards. Connect your host computer automatically to Xilinx, Intel^®, and Microchip^® FPGA boards over Ethernet, JTAG, or PCI Express^®.

Documentation | Examples

Screenshot of the HDL Workflow Advisor verifying generated HDL from HDL Coder.

Integrate with HDL Code Generation

Perform automated verification of HDL code generated by HDL Coder™ from the HDL Workflow Advisor tool using HDL cosimulation or FPGA-in-the-loop testing.

Documentation | Examples

AXI Manager

Access on-board memories from MATLAB or Simulink over JTAG, Ethernet, or PCI Express. Test FPGA algorithms via read or write access to AXI registers and transfer large signal or image files between MATLAB or Simulink and on-board memory locations.

Documentation | Examples (Xilinx, Intel)

FPGA Data Capture

Capture high-speed signals from designs executing on an FPGA and automatically load them into MATLAB for viewing and analysis. Analyze signals throughout your design to verify expected behavior or investigate anomalies.

Documentation | Examples

TLM Generation

Generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations.

Documentation | Examples

Product Resources:

Documentation Code examples Videos Requirements Release notes Supported EDA tools and hardware

“Simulink allows for us to reduce time spent on hand-writing production UVM test benches, test sequences and scoreboards by about 50% - leaving more time for us to focus on application for breakthrough innovations. Our ASICs designed for automotive applications rely on UVM for production verification – MATLAB and Simulink simplify the once tedious task of developing the algorithms for these devices.”
Khalid Chishti, ASIC development manager, Allegro MicroSystems