Signal Conversion
Convert signal to new type without altering signal values
Libraries:
Simulink /
Signal Attributes
HDL Coder /
Signal Attributes
Alternative Configurations of Signal Conversion Block:
Signal Copy | To Virtual Bus | To Nonvirtual Bus
Description
The Signal Conversion block converts a signal from one type to another. To select the type of conversion to perform, use the Output parameter or one of the preconfigured Signal Conversion blocks:
Signal Copy block
To Virtual Bus block
To Nonvirtual Bus block
Examples
Create Contiguous Copy of Bus
Use the Signal Conversion block to create a contiguous copy of a bus.
The Bus Creator block creates a nonvirtual bus that is input to the Signal Conversion block. With the Output parameter set to Signal copy
, the Signal Conversion block creates another contiguous copy of that input bus.
Convert Virtual Bus to Nonvirtual Bus
Use the Signal Conversion block to convert a virtual bus to a nonvirtual bus.
The Bus Creator block creates a virtual bus that is input to the Signal Conversion block. To convert the virtual bus to a nonvirtual bus, the Signal Conversion block has its Output parameter set to Nonvirtual bus
and its Data type parameter set to a Simulink.Bus
object. The specified Bus
object matches the bus hierarchy of the bus from the Bus Creator block. The nonvirtual bus output from the Signal Conversion block is input to the Bus Selector block.
Convert Nonvirtual Bus to Virtual Bus
Use the Signal Conversion block to convert a nonvirtual bus to a virtual bus.
The Bus Creator block creates a nonvirtual bus that is input to the Signal Conversion block. To convert the nonvirtual bus to a virtual bus, the Output parameter of the Signal Conversion block is set to Virtual bus
. The virtual bus output from the Signal Conversion block is input to the Bus Selector block.
Convert Mux Signal to Vector
Use the Signal Conversion block to convert a mux signal to a vector.
The Mux block creates a mux signal that is input to the Signal Conversion block. To convert the mux signal to a vector, the Output parameter of the Signal Conversion block is set to Signal copy
. The vector output from the Signal Conversion block is input to the Display block.
Ports
Input
Port_1 — Input signal to convert
scalar | vector | matrix | array | bus
The input signal is a scalar, vector, matrix, array, or bus that this block converts to another type.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| string
| Boolean
| fixed point
| enumerated
| bus
| image
Output
Port_1 — Converted signal
scalar | vector | matrix | array | bus
The output signal is the input signal converted to the specified type.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
| enumerated
| bus
| image
Parameters
To edit block parameters interactively, use the Property Inspector. From the Simulink® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.
Output — Type of conversion
Signal copy
| Virtual bus
| Nonvirtual bus
Specify the type of conversion to perform.
Signal copy
— Create a contiguous copy of the input signal. This value is the default value for the Signal Conversion and Signal Copy blocks.Virtual bus
— Convert a nonvirtual bus to a virtual bus. This value is the default value for the To Virtual Bus block.Nonvirtual bus
— Convert a virtual bus to a nonvirtual bus. This value is the default value for the To Nonvirtual Bus block.
For the Signal copy
option, the type of input determines how
the block makes the copy.
For example, suppose the block receives a mux signal, which has elements that occupy discontiguous areas of memory. The conversion allocates a contiguous area of memory for the elements of the mux signal and copies the values from the discontiguous areas represented by the block input to the contiguous areas represented by the block output at each time step. The output is a vector with elements that occupy contiguous areas of memory.
The type of conversion that you use depends on your modeling goal.
Modeling Goal | Option |
---|---|
Reduce generated code for a muxed signal. For an example involving Simulink Coder™ software, see Generate Reentrant Code from Subsystems (Simulink Coder). | Signal copy |
Connect a block with a constant sample time to an output port of an enabled subsystem. | Signal copy |
Save memory by converting a nonvirtual bus to a virtual bus. | Virtual bus |
Pass a virtual bus to a modeling construct that requires a nonvirtual bus. | Nonvirtual bus |
Create a copy of an array of buses. The block cannot convert an array of buses to a nonvirtual or virtual bus. To extract a bus from an array of buses, use a Selector block. | Signal copy |
Programmatic Use
To set the block parameter value programmatically, use
the set_param
function.
Parameter: | ConversionOutput |
Values: | 'Signal copy' (default) | 'Virtual bus' | 'Nonvirtual bus' |
Example: set_param(gcb,'ConversionOutput','Virtual
bus')
Data type — Nonvirtual bus data type
Inherit: auto
(default) | Bus: <object name>
| <data type expression>
Specify the output data type of the nonvirtual bus that this block produces.
Inherit: auto
— Inherit the data type from an upstream block. For example, inherit theSimulink.Bus
object data type from an upstream Bus Creator block.Bus: <object name>
or<data type expression>
— Specify aSimulink.Bus
object that matches the hierarchy of the input bus. If an upstream Bus Creator block specifies a bus object, specify the same bus object.
The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.
Dependencies
To enable this parameter, set Output to Nonvirtual
bus
.
Programmatic Use
To set the block parameter value programmatically, use
the set_param
function.
Parameter: | OutDataTypeStr |
Values: | 'Inherit: auto' (default) | 'Bus: <object name>' | '<data type expression>' |
Example: set_param(gcb,'OutDataTypeStr','Bus:
myBusObj')
Exclude this block from 'Block reduction' optimization — Option to exclude block from block reduction optimization
off
(default) | on
When the elements of the input signal occupy contiguous areas of memory, by default, the software eliminates this block from the compiled model as an optimization. For more information, see Block reduction.
To prevent this block from being eliminated from the compiled model, select this parameter.
Changes to this parameter take effect the next time you compile the model.
Dependencies
To enable this parameter, set Output
to Signal copy
.
Programmatic Use
To set the block parameter value programmatically, use
the set_param
function.
Parameter: | OverrideOpt |
Values: | 'off' (default) | 'on' |
Example: set_param(gcb,'OverrideOpt','on')
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Alternative Configurations
Signal Copy — Duplicate input signal
The Signal Copy block differs from the Signal Conversion block in name only.
Libraries:
Simulink /
Quick Insert /
Signal Attributes
To Virtual Bus — Convert nonvirtual bus to virtual bus
The To Virtual Bus block sets Output to
Virtual bus
.
Libraries:
Simulink /
Quick Insert /
Signal Attributes
To Nonvirtual Bus — Convert virtual bus to nonvirtual bus
The To Nonvirtual Bus block sets Output to
Nonvirtual bus
.
Libraries:
Simulink /
Quick Insert /
Signal Attributes
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a pass-through implementation.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
This block supports code generation for complex signals.
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
Version History
Introduced before R2006a
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