How HDL Coder can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either certain block implementations or by optimizations for the purpose of improving the efficiency of the hardware implementations. However, introducing delays on only certain paths can result functional behavior that is different from the original intent of the user model, thereby violating functional equivalence between the original user model and the HDL implementation.

Balance delays in specific parts of a design, without balancing delays on the entire design.

Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see the enable-based multicycle path constraints documentation.

How an indiscrete usage of Simulate rates on a multi- rate design can generate an undesirable HDL code, and provides few recommendations for optimal code generation.