Data Capture Workflow

Use FPGA data capture to observe signals from your design while the design is running on the FPGA. The FPGA data capture feature captures a window of signal data from the FPGA and returns the data to MATLAB^® or Simulink^® over a JTAG, Ethernet, or USB Ethernet interface.

FPGA data capture over a JTAG connection is available for Intel^® and AMD^® devices. FPGA data capture over an Ethernet or USB Ethernet connection is available for AMD devices only. For a complete list of supported devices and interfaces, see Supported FPGA Devices for FPGA Verification.

You can use one of two workflows to capture data from your FPGA or SoC device and send it to MATLAB or Simulink:

• HDL Coder™ Workflow — When you generate the HDL IP with HDL Coder, use the HDL Workflow Advisor tool to generate the data capture IP and integrate it in the design.

• Existing HDL Design — If you have an existing HDL design, use HDL Verifier™ tools to generate the data capture IP. Then, manually integrate the generated IP into your FPGA design.

  When you use this workflow, you can configure the memory type for storing captured data as external memory. You can capture large datasets up to two gigasamples by utilizing the external DDR memory connected to the FPGA for an AMD device over a JTAG connection.

In both workflows, to capture signals from your design, HDL Verifier generates an IP core that communicates with MATLAB. Use the HDL Coder workflow to automatically integrate the data capture IP core in your design. Otherwise, manually integrate this IP core into your HDL project and deploy it to the FPGA along with the rest of your design. Then, use one of the following methods to capture data.

• Capture data and send it to MATLAB — HDL Verifier generates a customized tool that returns the captured signal data. Alternatively, you can use the generated System object™ to capture data programmatically.

• Capture data and send it to Simulink — HDL Verifier generates a block that has output ports corresponding to the signals you captured.

In both cases, you can specify data types for the captured data, number of windows to capture, trigger condition that control when to capture the data, and capture condition that control which data to capture.

When the design is running on the FPGA, first the generated IP core waits for the trigger condition. Define a trigger condition that initiates when the values of one or more signals match the specified criteria. When the IP core detects the trigger, the logic captures the designated signals in a buffer and returns the data over the JTAG, Ethernet, or USB Ethernet interface to the host machine. You can then analyze and display these signals in your MATLAB workspace or Simulink model.

To make the best use of the buffer size and capture only the valid data, you can also define a capture condition. Define a capture condition in the same way as you define the trigger condition. When both the conditions are satisfied, the logic captures only the valid values of the designated signals.

Generate and Integrate Data Capture IP Using HDL Workflow Advisor

When you use the HDL Workflow Advisor tool to generate your HDL design, first mark interesting signals as test points in Simulink. Configure your design using the HDL Workflow Advisor tool to:

• Select the type of connection channel by setting the FPGA Data Capture (HDL Verifier required) parameter in the Set Target Reference Design task. For more information, see Set Target Reference Design (HDL Coder).

• Enable test point generation by selecting the Enable HDL DUT port generation for test points parameter in the Set Target Interface task. For more information, see Set Target Interface (HDL Coder).

• Connect test point signals to the FPGA Data Capture interface in the Set Target Interface task.

• Set up buffer size and maximum sequence depth for data collection in the Generate RTL Code and IP Core task. To include capture condition logic in the IP core, select Include capture condition logic in FPGA Data Capture. For more information, see Generate RTL Code and IP Core (HDL Coder).

Then, run through the remaining steps to generate HDL code for your design and program the FPGA. The data capture IP core is integrated in the generated design. You are now ready to Capture Data.

Configure and Generate IP Core for Existing HDL Design

Before you can capture FPGA data, first specify which signals to capture and how many samples to return. Use the FPGA Data Capture Component Generator to configure these and other settings and to generate the HDL IP core. The IP core contains:

• A port for each signal you want to capture or use as part of a trigger condition

• Memory to capture the number of samples you requested for each signal

• JTAG or Ethernet interface logic to communicate with MATLAB

• Trigger and capture condition logic that you can configure at run time

• A ready-to-capture signal to control data flow from the FPGA

The tool also generates a customized FPGA Data Capture tool, System object, and model that communicate with the FPGA.

Integrate IP into FPGA

For MATLAB to communicate with the FPGA, you must integrate the generated HDL IP core into your FPGA design. If you used the HDL Workflow Advisor tool to generate your data capture IP, this step is automated. In this case, data capture IP operates on a single-clock rate, which is the primary clock of your device under test (DUT). If you did not use the HDL Workflow Advisor tool, follow the instructions in the generation report based on your device family.

Intel Devices

Follow these instructions to integrate the datacapture HDL IP core into your FPGA design that targets an Intel device.

1. Create a Quartus^® project.

2. Navigate to the hdlsrc folder.

3. Add the generated HDL files in the hdlsrc folder to your Quartus project. Then, instantiate the HDL IP core, datacapture, in your HDL code. Connect datacapture to the signals selected for data capture and specifying the triggers.

4. Compile the project and program the FPGA with the new image through a JTAG connection.

AMD Non-Versal Devices

Follow these instructions to integrate the data capture HDL IP core into your FPGA design that targets an AMD non-Versal^® device.

1. Create a Vivado^® project.

2. Follow one of these steps based on your connection type.

    JTAG with internal memory

   Follow these instructions if you set Connection type to JTAG and Storage type to Internal memory in the FPGA Data Capture Component Generator tool.

   1. Add the generated data capture IP core and JTAG Debug Hub IP in the hdlsrc folder to the user repository of your Vivado project by executing this command in MATLAB. The JTAG Debug Hub IP communicates with MATLAB on the host machine and with the data capture IP in the FPGA design.

      addFPGADataCaptureToVivado("vivadoProjectPath",DataCaptureIPFolder="destinationFolder");

      vivadoProjectPath is the name of Vivado project location and destinationFolder is the name of the folder that contains the generated data capture IP.

      For example, the following command adds the data capture IP and JTAG Debug Hub IP in the hdlsrc folder to the C:\test_design_zc706\hdl_prj\vivado_ip_prj\vivado_prj.xpr Vivado project.

      addFPGADataCaptureToVivado("C:\test_design_zc706\hdl_prj\vivado_ip_prj\vivado_prj.xpr", ...
      DataCaptureIPFolder="hdlsrc");

   2. Open the Vivado project, then open your block design. Insert the data capture IP and JTAG Debug Hub IP into your block design.

   3. Connect the BSCAN subordinate (BSCAN_S) interface of the data capture IP to the BSCAN manager (BSCAN_M) interface of the JTAG Debug Hub IP.

   4. Connect the dc_active output port of the data capture IP to the active_s1 input port of the JTAG Debug Hub IP. The JTAG Debug Hub IP controls the data capture IP by using this active signal.

      

   5. Connect data capture IP to the signals selected for data capture and specifying the triggers.

   6. Complete the block design by connecting the clk and clk_enable input ports of the data capture IP.

    JTAG with external memory

   Follow these instructions if you set Connection type to JTAG and Storage type to External memory in the FPGA Data Capture Component Generator tool.

   Note

   FPGA data capture support for external memory is available for AMD devices over JTAG connections only.

   1. Add the generated data capture IP core and JTAG Debug Hub IP in the hdlsrc folder to the user repository of your Vivado project by executing this command in MATLAB. The JTAG Debug Hub IP communicates with MATLAB on the host machine and with the data capture IP in the FPGA design.

      addFPGADataCaptureToVivado("vivadoProjectPath",DataCaptureIPFolder="destinationFolder");

      vivadoProjectPath is the name of Vivado project location and destinationFolder is the name of the folder that contains the generated data capture IP.

      For example, the following command adds the data capture IP and JTAG Debug Hub IP in the hdlsrc folder to the C:\test_design_zc706\hdl_prj\vivado_ip_prj\vivado_prj.xpr Vivado project.

      addFPGADataCaptureToVivado("C:\test_design_zc706\hdl_prj\vivado_ip_prj\vivado_prj.xpr", ...
      DataCaptureIPFolder="hdlsrc");

   2. Open the Vivado project, then open your block design. Insert the data capture IP and JTAG Debug Hub IP into your block design.

   3. Connect the BSCAN subordinate (BSCAN_S) interface of the data capture IP to the BSCAN manager (BSCAN_M) interface of the JTAG Debug Hub IP.

   4. Connect the dc_active output port of the data capture IP to the active_s1 input port of the JTAG Debug Hub IP. The JTAG Debug Hub IP controls the data capture IP by using this active signal.

   5. Connect the AXI4 manager (AXI4_M) interface of the data capture IP to the AXI4 subordinate (S_AXI) interface of MIG through AXI Interconnect, as this figure shows.

      

   6. Connect data capture IP to the signals selected for data capture and specifying the triggers.

   7. Complete the block design by connecting the clk, reset, clk_enable, m_dest_axi_aclk, and m_dest_axi_aresetn input ports of the data capture IP.

   8. Make sure that the m_dest_axi_aclk, used by the data capture IP to write data to external DDR memory, has a higher frequency than the clk clock.

    PL Ethernet

   Follow these instructions if you set Connection type to PL Ethernet in the FPGA Data Capture Component Generator tool.

   1. Open the Vivado project.

   2. Navigate to the hdlsrc folder in the Vivado Tcl console.

   3. Create a Vivado block design with the data capture IP and Ethernet MAC Hub IP by executing this command in the Vivado Tcl console.

      source ./insertEthernet.tcl

      The insertEthernet Tcl script generates this block design:

      

   4. Connect the data capture IP to the signals selected for data capture and specifying the triggers.

   5. Complete the block design by connecting the clk and clk_enable input ports of the data capture IP.

    PS Ethernet or USB Ethernet

   Follow these instructions if you set Connection type to PS Ethernet or USB Ethernet in the FPGA Data Capture Component Generator tool.

   Note

   For PS Ethernet and USB Ethernet interfaces, you must set up the target SoC device and the host computer before you perform the data capture operations. For more information, see Capture Data over PS Ethernet for PS Ethernet and Capture Data over USB Ethernet for USB Ethernet.

   1. Add the generated data capture IP in the hdlsrc folder to the user repository of your Vivado project by executing this command in MATLAB.

      addFPGADataCaptureToVivado("vivadoProjectPath",DataCaptureIPFolder="destinationFolder");

      vivadoProjectPath is the name of Vivado project location and destinationFolder is the name of the folder that contains the generated data capture IP.

      For example, the following command adds the data capture IP in the hdlsrc folder to the C:\test_design_zc706\hdl_prj\vivado_ip_prj\vivado_prj.xpr Vivado project.

      addFPGADataCaptureToVivado("C:\test_design_zc706\hdl_prj\vivado_ip_prj\vivado_prj.xpr", ...
      DataCaptureIPFolder="hdlsrc");

   2. Open the Vivado project. Then, open your block design and insert the data capture IP into it.

   3. Connect the subordinate AXI4 interface of the data capture IP to the manager AXI4 interface of the processor.

      

   4. Connect data capture IP to the signals selected for data capture and specifying the triggers.

   5. Complete the block design by connecting the clk, clk_enable, IPCORE_RESETN, AXI4_ACLK, and AXI4_ARESETN input ports of the data capture IP.

3. JTAG or PL Ethernet only — Compile the project and program the FPGA with the new image through a JTAG or Ethernet connection.

   PS Ethernet or USB Ethernet only — Use the loadBitstream function to load the BIT and DTB files based on your FPGA design. For the steps to generate a device tree blob (DTB) file, follow the instructions in the generation report. For more information about DTB file generation steps, see Generate DTB File.

AMD Versal Devices

Follow these instructions to integrate the data capture HDL IP core into your FPGA design targeted on an AMD Versal device.

Note

FPGA data capture support for Versal devices is available for JTAG connections only.

1. Open your block design in Vivado.

2. Navigate to the hdlsrc folder in the Vivado Tcl console.

3. Follow one of these steps based on your storage type.

    JTAG with internal memory

   Follow these instructions if you set Connection type to JTAG and Storage type to Internal memory in the FPGA Data Capture Component Generator tool.

   1. Insert the data capture IP into your block design and connect the IP to the BSCAN_USER2 interface of the AMD Versal platform CIPS IP by executing this command in the Vivado Tcl console.

      source ./insertVersalFPGADataCaptureIP.tcl

      To enable the BSCAN_USER2 interface, enable the PL BSCAN1 interface in the CIPS IP.

      

   2. Connect data capture IP to the signals selected for data capture and specifying the triggers.

   3. Complete the block design by connecting the clk and clk_enable input ports of the data capture IP.

    JTAG with external memory

   Follow these instructions if you set Connection type to JTAG and Storage type to External memory in the FPGA Data Capture Component Generator tool.

   1. Insert the data capture IP into your block design and connect the IP to the BSCAN_USER2 interface of the AMD Versal platform CIPS IP by executing this command in the Vivado Tcl console.

      source ./insertVersalFPGADataCaptureIP.tcl

      To enable the BSCAN_USER2 interface, enable the PL BSCAN1 interface in the CIPS IP.

      

   2. Connect the AXI4 manager (m_dest_axi) interface of the data capture IP to the AXI4 subordinate (S_AXI) interface of the AMD AXI NoC IP, as this figure shows.

      

   3. Connect data capture IP to the signals selected for data capture and specifying the triggers.

   4. Complete the block design by connecting the clk, reset, clk_enable, m_dest_axi_aclk, and m_dest_axi_aresetn input ports of the data capture IP.

   5. Make sure that m_dest_axi_aclk, used by the data capture IP to write data to external DDR memory, has a higher frequency than the clk clock.

4. Compile the project and program the FPGA with the new image through a JTAG cable.

Capture Data

The FPGA data capture IP core communicates over the JTAG, Ethernet, or USB cable between your FPGA board and the host computer. Make sure that the required cable is connected. Before capturing data, you can set data types for the captured data, set a trigger condition that specifies when to capture the data, and set a capture condition that specifies the data to be captured. To configure these options and capture data, you can:

• Open the FPGA Data Capture tool. Set the trigger, capture condition, and data type parameters, and then capture data into the MATLAB workspace.

• Use the generated System object derived from hdlverifier.FPGADataReader. Set the data types, trigger condition, and capture condition using the methods and properties of the System object, and then call the object to capture data.

• In Simulink, open the generated model and configure the parameters of the FPGA Data Reader block. Then run the model to capture data.

Set Base Address of External DDR Memory (for JTAG with External Memory Only)

For JTAG with external memory, set the base address of the external DDR memory. To do this, use the MemoryBaseAddress property of the hdlverifier.FPGADataReader System object before capturing data to MATLAB. Set the External DDR memory base address parameter of the FPGA Data Reader block before capturing data to Simulink.

For example, the following command sets the base address of the DDR memory for the datacapture1 System object to 80000000.

datacapture1.MemoryBaseAddress = "80000000";

Set Base Address of Data Capture IP and IP Address of Target Device (for PS Ethernet and USB Ethernet Only)

For PS Ethernet and USB Ethernet, set the base address of the data capture IP and the IP address of the target device. To do this, use the CaptureBaseAddress and DeviceAddress properties of the hdlverifier.FPGADataReader System object before capturing data to MATLAB. Set the Device IP address and Data Capture IP core base address parameters of the FPGA Data Reader block before capturing data to Simulink.

For example, the following commands set the base address of the datacapture1 data capture IP to 40000000 and the IP address of the target device to 192.168.5.2.

datacapture1.CaptureBaseAddress = "40000000";
datacapture1.DeviceAddress = "192.168.5.2";

After you capture the data and import it into the MATLAB workspace or Simulink model, you can analyze, verify, and display the data.

For an AMD device over a JTAG connection, you can observe signals operating at different clock rates by using multiple data capture IPs. For more information about how to generate and integrate multiple data capture IPs into your FPGA design, see Capture Asynchronous Data.