Carrier Synchronizer

Compensate for carrier frequency offset

• 

Libraries:
Communications Toolbox / Synchronization

Description

The Carrier Synchronizer block compensates for carrier frequency and phase offsets in signals that use single-carrier modulation schemes. The carrier synchronizer algorithm is compatible with BPSK, QPSK, OQPSK, 8-PSK, PAM, and rectangular QAM modulation schemes.

Note

Modulation-type dependent phase ambiguities may be introduced by the synchronization algorithm. For more information, see Potential Phase Ambiguity.

This icon shows the block without optional port.

Examples

Correct for Frequency and Phase Offset

Correct for a phase and frequency offset imposed on a noisy 16-QAM channel by using the Carrier Synchronizer block.

The doc_qamcarriersync model configures a 16-QAM signal, adds phase and frequency offset, passes the signal through a noisy AWGN channel, and then corrects the offsets by using the Carrier Synchronizer block.

The constellation diagram shows the signal constellation before and after carrier synchronization. Before synchronization, the signal appears as a spiral pattern that results from a phase and frequency offset. After the carrier synchronizer converges to a solution, the signal symbols are grouped around the reference constellation.

Experiment with the parameters in the Phase/Frequency Offset and Carrier Synchronizer blocks. By varying these parameters, you can change how quickly the output conforms to an ideal 16-QAM constellation. If the signal does not converge to the expected constellation, additional measures can be taken to achieve successful recovery.

Resolve Symbol Phase Ambiguity From Carrier Synchronization

While correcting for a phase and frequency offset imposed on a QPSK signal, the Carrier Synchronizer block introduces symbol phase ambiguity that increases the symbol error rate (SER). To resolve the symbol phase ambiguity, this example adds a frame preamble to the transmitted signal and includes a subsystem block that computes the phase ambiguity introduced by the carrier synchronization.

The doc_carrsync_resolve_ambig model configures a QPSK-modulated data frame that includes a Barker sequence preamble and random data. The data frame gets impaired by phase and frequency offsets and an AWGN channel. A Phase/Frequency Offset block sets the phase offset to 45 degrees and frequency offset to 1 kHz. The frequency offset is 1% of the 10 kHz sample rate. A Carrier Synchronizer block corrects the offsets but introduces symbol phase ambiguity that results in a poor symbol error rate (SER).

The model initializes variables used to configure block parameters by using the InitFcn callback function. For more information, see Model Callbacks (Simulink).

The constellation diagram shows the transmitted signal along with the signal constellation before and after carrier synchronization. Before synchronization, the phase and frequency offset cause the constellation points to shift around outlining a circle. After the carrier synchronizer converges to a solution, the signal symbols are grouped around the reference constellation but there may be a symbol phase ambiguity in the placement of constellation points that results in symbol errors. The model computes the SER before and after resolution of symbol phase ambiguity. Removing the phase ambiguity reduces the SER dramatically.

Ports

Input

In — Input signal

scalar | column vector

Input signal, specified as a scalar or vector.

This port is unnamed on the block.

Data Types: double | single
Complex Number Support: Yes

Output

Out — Phase corrected output signal

scalar | column vector

Phase corrected output signal, returned as a scalar or column vector with the same data type and length as the input signal. The output signal adjusts the input signal compensating for carrier frequency and phase offsets in signals that use single-carrier modulation schemes.

This port is unnamed on the block until the Estimated phase error output port parameter is selected.

Data Types: double | single
Complex Number Support: Yes

phEst — Phase estimate in radians

scalar | column vector

Phase estimate in radians, returned as a scalar or column vector with the same length as the input signal.

Dependencies

To enable this port, select the Estimated phase error output port parameter.

Data Types: double | single

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Modulation — Modulation type

QAM (default) | 8PSK | BPSK | OQPSK | PAM | QPSK

Modulation type, specified as QAM, 8PSK, BPSK, OQPSK, PAM, or QPSK.

Modulation phase offset — Modulation phase offset method

Auto (default) | Custom

Modulation phase offset method, specified as Auto or Custom.

• Auto — Apply the traditional offset for the specified modulation type.

  Modulation	Phase Offset (radians)
  BPSK, QAM, or PAM	0
  OQPSK or QPSK	π/4
  8PSK	π/8

• Custom — Specify a user-defined phase offset with the CustomPhaseOffset property.

Tunable: Yes

Custom phase offset (radians) — Custom phase offset

0 (default) | scalar

Custom phase offset in radians, specified as a scalar.

Dependencies

This parameter applies when you set Modulation phase offset to Custom.

Samples per symbol — Number of samples per symbol

2 (default) | positive integer

Number of samples per symbol, specified as a positive integer.

Tunable: Yes

Damping factor — Damping factor of loop

0.707 (default) | positive scalar

Damping factor of the loop, specified as a positive scalar.

Tunable: Yes

NormalizedLoopBandwidth — Normalized bandwidth of loop

0.01 (default) | scalar

Normalized bandwidth of the loop, specified as a scalar in the range (0,1]. The loop bandwidth is normalized by the sample rate of the synchronizer.

Decreasing the loop bandwidth reduces the synchronizer convergence time but also reduces the pull-in range of the synchronizer.

Tunable: Yes

Estimated phase error output port — Enable estimated phase error output port

on (default) | off

Select this check box to provide the estimated phase error to output port phEst.

Simulate using — Type of simulation to run

Code generation (default) | Interpreted execution

Type of simulation to run, specified as Code generation or Interpreted execution.

• Code generation — Simulate the model by using generated C code. The first time you run a simulation, Simulink generates C code for the block. The model reuses the C code for subsequent simulations unless the model changes. This option requires additional startup time, but the speed of the subsequent simulations is faster than with the Interpreted execution option.

• Interpreted execution — Simulate the model by using the MATLAB^® interpreter. This option shortens startup time, but the speed of subsequent simulations is slower than with the Code generation option. In this mode, you can debug the source code of the block.

For more information, see Interpreted Execution vs. Code Generation (Simulink).

Block Characteristics

Data Types	double | single
Multidimensional Signals	no
Variable-Size Signals	yes

More About

Potential Phase Ambiguity

This table indicates the potential phase ambiguity that may be introduced by the synchronizer depending on the modulation type:

Modulation type	Phase Ambiguity (radians)
BPSK or PAM	0, π
OQPSK, QPSK, or QAM	0, π/2, π, 3π/2
8PSK	0, π/4, π/2, 3π/4, π, 5π/4, 3π/2, 7π/4

For best results, apply carrier synchronization to non-oversampled signals.

Algorithms

The algorithm implements a closed-loop compensator that uses the PLL-based algorithm described in [1]. The output of the synchronizer, y_n, is a frequency-shifted version of the complex input signal, x_n, for the nth sample. The synchronizer output is $$y_{\text{n}}=x_{\text{n}}{e}^{i{\lambda }_{\text{n}}},$$where λ_n is the output of the direct digital synthesizer (DDS). The DDS is the discrete-time version of a voltage-controlled oscillator and is a core component of discrete-time phase locked loops. The DDS works as an integration filter.

To correct for the frequency offset, first the algorithm determines the phase error, e_n. The value of the phase error depends on the modulation scheme.

Modulation	Phase Error
QAM or QPSK	$$e_{\text{n}}=\mathrm{sgn}\left(\mathrm{Re}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Im}\left\{x_{\text{n}}\right\}-\mathrm{sgn}\left(\mathrm{Im}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Re}\left\{x_{\text{n}}\right\}$$ For a detailed description of this equation, see [1].
BPSK or PAM	$$e_{\text{n}}=\mathrm{sgn}\left(\mathrm{Re}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Im}\left\{x_{\text{n}}\right\}$$ For a detailed description of this equation, see [1].
8-PSK	$$e_{\text{n}}=\{\begin{array}{c}\mathrm{sgn}\left(\mathrm{Re}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Im}\left\{x_{\text{n}}\right\}-\left(\sqrt{2}-1\right)\mathrm{sgn}\left(\mathrm{Im}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Re}\left\{x_{\text{n}}\right\}\text{,}\text{for}\left|\mathrm{Re}\left\{x_{\text{n}}\right\}\right|\ge \left|\mathrm{Im}\left\{x_{\text{n}}\right\}\right|\\ \left(\sqrt{2}-1\right)\mathrm{sgn}\left(\mathrm{Re}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Im}\left\{x_{\text{n}}\right\}-\mathrm{sgn}\left(\mathrm{Im}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Re}\left\{x_{\text{n}}\right\}\text{,}\text{for}\left|\mathrm{Re}\left\{x_{\text{n}}\right\}\right|<\left|\mathrm{Im}\left\{x_{\text{n}}\right\}\right|\end{array}$$ For a detailed description of this equation, see [2].
OQPSK	$$e_{\text{n}}=\mathrm{sgn}\left(\mathrm{Re}\left\{x_{\text{n-SamplePerSymbol/2}}\right\}\right)\times \mathrm{Im}\left\{x_{\text{n-SamplePerSymbol/2}}\right\}-\mathrm{sgn}\left(\mathrm{Im}\left\{x_{\text{n}}\right\}\right)\times \mathrm{Re}\left\{x_{\text{n}}\right\}$$

To ensure system stability, the phase error passes through a biquadratic loop filter governed by

$${\psi }_{\text{n}}=g_{\text{I}}{e}_{\text{n}}+{\psi }_{\text{n}-1},$$

where ψ_n is the output of the loop filter at sample n, and g_I is the integrator gain. The integrator gain is determined from the equation

$$g_{\text{I}}=\frac{4\left({\theta }^2/d\right)}{K_{\text{p}}{K}_{\text{0}}},$$

where

• $$\theta \text{=}\frac{B_{\text{n}}T}{\left(\zeta +\frac{1}{4\zeta }\right)}\text{and}d=1+2\zeta \theta +{\theta }^2,$$

• B_n is the normalized loop bandwidth

• ζ is the damping factor

• K₀ is the phase recovery gain and equals the number of samples per symbol.

• K_p is the phase error detector gain and is determined by the modulation type.

Modulation	Kp
BPSK, PAM, QAM, QPSK, or OQPSK	2
8-PSK	1

The output of the loop filter is then passed to the DDS. The DDS is another biquadratic loop filter whose expression is based on the forward Euler integration rule

$${\lambda }_{\text{n}}=\left(g_{\text{P}}{e}_{\text{n-1}}+{\psi }_{\text{n-1}}\right)+{\lambda }_{\text{n-1}},$$

where g_P is the proportional gain that is expressed as

$$g_{\text{P}}=\frac{4\zeta \left(\theta /d\right)}{K_{\text{p}}{K}_{\text{0}}}.$$

The info object function returns estimates of the normalized pull-in range, the maximum frequency lock delay, and the maximum phase lock delay. The normalized pull-in range, (Δf)_pull-in, is expressed in radians and estimated as

$${\left(\Delta f\right)}_{\text{pull-in}}\approx \min \left(1,2\pi \sqrt{2}\zeta B_{\text{n}}\right).$$

The expression for (Δf )_pull-in becomes less accurate as $$2\pi \sqrt{2}\zeta B_{\text{n}}$$ approaches 1.

The maximum frequency lock delay, T_FL, and phase lock delay, T_PL, are expressed in samples and estimated as

$$T_{\text{FL}}\approx 4\frac{{\left(\Delta f\right)}_{\text{pull-in}}^2}{B_{\text{n}}^3}\text{and}{T}_{\text{PL}}\approx \frac{1.3}{B_{\text{n}}}.$$

References

[1] Rice, Michael. Digital Communications: A Discrete-Time Approach. Upper Saddle River, NJ: Prentice Hall, 2008. pp. 359–393.

[2] Huang Zhijie, Yi Zhiqiang, Zhang Ming and Wang Kuang, "8PSK demodulation for new generation DVB-S2," 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914), Chengdu, 2004, pp. 1447-1450 Vol.2, doi: 10.1109/ICCCAS.2004.1346447.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2015a