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AXI Manager

Access AXI subordinate memory on FPGA board from MATLAB® or Simulink®


MATLAB AXI master has been renamed to AXI manager. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.

Access on-board memory locations from MATLAB or Simulink by using the AXI manager IP in your FPGA design. This IP connects to subordinate memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express®, or Ethernet cable.

To use this feature, you must download a hardware support package for your FPGA board. More documentation for this feature is included with the support package installation. See support package documentation:

  • AXI Manager (HDL Verifier Support Package for Intel FPGA Boards)

  • AXI Manager (HDL Verifier Support Package for Xilinx FPGA Boards)

For information on downloading support packages, see Download FPGA Board Support Package.



AXI Manager Requirements and Preparation

  • Download FPGA Board Support Package
    The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation, FPGA data capture, or AXI manager.
  • Set Up FPGA Design Software Tools
    Set the MATLAB path to Xilinx®, Microchip, and Intel® software.
  • Guided Hardware Setup
    Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop, AXI manager, or FPGA data capture.