Use the distributed pipelining and loop unrolling optimizations in HDL Coder to optimize clock speed.

Use the RAM mapping optimization in HDL Coder™ to map persistent matrix variables to block RAMs in hardware.

Use the resource sharing optimization in HDL Coder™. This optimization identifies functionally equivalent multiplier operations in MATLAB® code and shares them in order to optimize design area. You have control over the number of multipliers to be shared in the design.

Use the design-level loop streaming optimization in HDL Coder™ to optimize area.

Perform a design-level area optimization in HDL Coder™ by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The CSD representation of multiplier constants for example, in gain coefficients or filter coefficients) significantly reduces the area of the hardware implementation.