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UVM テストベンチで動作 DUT を RTL DUT に置き換える
この例では、代替の C ベースの設計 DUT から、単純な動作 RTL DUT インターフェイス、さらに AXI4-Lite および AXI4-Stream バス プロトコルを使用する完全なプロトコル ベースの RTL DUT インターフェイスに移行する方法を示します。ドライバーやモニターなど、いくつかの UVM コンポーネントを変更する必要がありますが、元のテストベンチ構造とシーケンスおよびスコアボード コンポーネントは変更せずに再利用できます。
設計の説明と UVM テストベンチ生成の背景については、Simulink からパラメータ化された UVM テストベンチを生成する の例を参照してください。
UVMテストベンチを生成する
まず、プロジェクトとモデルを開きます。
openProject('pulsedetector_proj'); model = 'pulsedetector_tb'; open_system(model);
この例のデフォルトの UVM テストベンチを生成するには、次を実行します。
design = [model '/PulseDetector']; sequence = [model '/GenPulse']; scoreboard = [model '/CheckDetection']; predictor = [model '/PulseDetectorRef']; driver = [model '/InputDriver']; monitor = [model '/OutputMonitor']; uvmbuild(design, sequence, scoreboard, Predictor=predictor, Driver=driver, Monitor=monitor);
### Starting DPI subsystem generation for UVM test bench ### Starting build procedure for model: PulseDetector ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper PulseDetector_dpi.h ### Generating DPI C Wrapper PulseDetector_dpi.c ### Generating UVM module package PulseDetector_dpi_pkg.sv ### Generating SystemVerilog module PulseDetector_dpi.sv ### Generating makefiles for: PulseDetector_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: PulseDetector Build Summary Top model targets built: Model Action Rebuild Reason =============================================================================================== PulseDetector Code generated and compiled. Code generation information file does not exist. 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 31.238s ### Starting build procedure for model: GenPulse ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper GenPulse_dpi.h ### Generating DPI C Wrapper GenPulse_dpi.c ### Generating UVM module package GenPulse_dpi_pkg.sv ### Generating SystemVerilog module GenPulse_dpi.sv ### Generating makefiles for: GenPulse_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: GenPulse Build Summary Top model targets built: Model Action Rebuild Reason ========================================================================================== GenPulse Code generated and compiled. Code generation information file does not exist. 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 26.802s ### Starting build procedure for model: InputDriver ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper InputDriver_dpi.h ### Generating DPI C Wrapper InputDriver_dpi.c ### Generating UVM module package InputDriver_dpi_pkg.sv ### Generating SystemVerilog module InputDriver_dpi.sv ### Generating makefiles for: InputDriver_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: InputDriver Build Summary Top model targets built: Model Action Rebuild Reason ============================================================================================= InputDriver Code generated and compiled. Code generation information file does not exist. 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 20.099s ### Starting build procedure for model: OutputMonitor ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper OutputMonitor_dpi.h ### Generating DPI C Wrapper OutputMonitor_dpi.c ### Generating UVM module package OutputMonitor_dpi_pkg.sv ### Generating SystemVerilog module OutputMonitor_dpi.sv ### Generating makefiles for: OutputMonitor_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: OutputMonitor Build Summary Top model targets built: Model Action Rebuild Reason =============================================================================================== OutputMonitor Code generated and compiled. Code generation information file does not exist. 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 21.032s ### Starting build procedure for model: CheckDetection ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper CheckDetection_dpi.h ### Generating DPI C Wrapper CheckDetection_dpi.c ### Generating UVM module package CheckDetection_dpi_pkg.sv ### Generating SystemVerilog module CheckDetection_dpi.sv ### Generating makefiles for: CheckDetection_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: CheckDetection Build Summary Top model targets built: Model Action Rebuild Reason ================================================================================================ CheckDetection Code generated and compiled. Code generation information file does not exist. 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 29.418s ### Starting build procedure for model: PulseDetectorRef ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper PulseDetectorRef_dpi.h ### Generating DPI C Wrapper PulseDetectorRef_dpi.c ### Generating UVM module package PulseDetectorRef_dpi_pkg.sv ### Generating SystemVerilog module PulseDetectorRef_dpi.sv ### Generating makefiles for: PulseDetectorRef_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: PulseDetectorRef Build Summary Top model targets built: Model Action Rebuild Reason ================================================================================================== PulseDetectorRef Code generated and compiled. Code generation information file does not exist. 1 of 1 models built (0 models already up to date) Build duration: 0h 0m 22.554s ### Starting UVM test bench generation for model: pulsedetector_tb ### Generating UVM transaction object ./uvm_build/pulsedetector_tb_uvm_testbench/scoreboard/mw_PulseDetector_scoreboard_trans.sv ### Generating UVM interface ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_if.sv ### Generating UVM sequence ./uvm_build/pulsedetector_tb_uvm_testbench/sequence/mw_PulseDetector_sequence.sv ### Generating UVM sequencer ./uvm_build/pulsedetector_tb_uvm_testbench/sequence/mw_PulseDetector_sequencer.sv ### Generating UVM sequence transaction ./uvm_build/pulsedetector_tb_uvm_testbench/sequence/mw_PulseDetector_sequence_trans.sv ### Generating UVM driver ./uvm_build/pulsedetector_tb_uvm_testbench/driver/mw_PulseDetector_driver.sv ### Generating UVM monitor ./uvm_build/pulsedetector_tb_uvm_testbench/monitor/mw_PulseDetector_monitor.sv ### Generating UVM input monitor ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_monitor_input.sv ### Generating UVM Reference Model ./uvm_build/pulsedetector_tb_uvm_testbench/predictor/mw_PulseDetector_predictor.sv ### Generating UVM transaction object ./uvm_build/pulsedetector_tb_uvm_testbench/predictor/mw_PulseDetector_predictor_trans.sv ### Generating UVM agent ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_agent.sv ### Generating UVM scoreboard ./uvm_build/pulsedetector_tb_uvm_testbench/scoreboard/mw_PulseDetector_scoreboard.sv ### Generating UVM scoreboard configuration object ./uvm_build/pulsedetector_tb_uvm_testbench/scoreboard/mw_PulseDetector_scoreboard_cfg_obj.sv ### Generating UVM environment ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_environment.sv ### Generating UVM test ./uvm_build/pulsedetector_tb_uvm_testbench/uvm_artifacts/mw_PulseDetector_test.sv ### Generating UVM top ./uvm_build/pulsedetector_tb_uvm_testbench/top/mw_PulseDetector_top.sv ### Generating UVM test package ./uvm_build/pulsedetector_tb_uvm_testbench/top/pulsedetector_tb_pkg.sv ### Generating UVM test bench simulation script for Mentor Graphics QuestaSim/Modelsim ./uvm_build/pulsedetector_tb_uvm_testbench/top/run_tb_mq.do ### Generating UVM test bench simulation script for Cadence Xcelium ./uvm_build/pulsedetector_tb_uvm_testbench/top/run_tb_xcelium.sh ### Generating UVM test bench simulation script for Synopsys VCS ./uvm_build/pulsedetector_tb_uvm_testbench/top/run_tb_vcs.sh
CベースのDUTをRTLベースのDUTに置き換える
UVM テストベンチ生成では、DUT を SystemVerilog モジュールにラップされた C ベースのアルゴリズムとしてエクスポートします。これにより、生成された UVM が元の Simulink® シミュレーション動作と一致するかどうかをすぐに確認できます。もちろん、UVM テストベンチの目的は、手書きか HDL Coder™ によって生成されたかに関係なく、RTL を検証することです。Simulink DUT インターフェイスが目的の RTL インターフェイスと一致する場合は、生成された UVM テストベンチで最小限のオーバーライドを使用して、C ベースの DUT を RTL に直接置き換えることができます。
動作インターフェース付きRTLを生成する
RTL を生成するために HDL Coder を使用しない場合は、overrides_RTLDUT/RTLIPSource のこの例で HDL ソースが利用できます。
HDL Coder を使用すると、DUT の RTL バージョンを直接作成できます。
makehdl(design, 'targetdirectory', 'rtl_no_protocols');
### Generating HDL for 'pulsedetector_tb/PulseDetector'. ### Using the config set for model pulsedetector_tb for HDL code generation parameters. ### Running HDL checks on the model 'pulsedetector_tb'. ### Begin compilation of the model 'pulsedetector_tb'... ### Begin compilation of the model 'pulsedetector_tb'... ### Working on the model 'pulsedetector_tb'... ### Starting Verilog code generation process for filter: filter ### 'LUTMapToRAM' is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware. To disable pipeline insertion for mapping lookup tables to RAM, please set the option to 'Off'. ### The code generation and optimization options you have chosen have introduced additional pipeline delays. ### The delay balancing feature has automatically inserted matching delays for compensation. ### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays. ### Output port 1: 8 cycles. ### Output port 2: 8 cycles. ### Working on... GenerateModel ### Begin model generation 'gm_pulsedetector_tb' .... ### Rendering DUT with optimization related changes (IO, Area, Pipelining)... ### Model generation complete. ### Begin Verilog Code Generation for 'pulsedetector_tb'. ### Working on pulsedetector_tb/PulseDetector/Create TDATA as rtl_no_protocols/pulsedetector_tb/Create_TDATA.v. ### Working on pulsedetector_tb/PulseDetector/Detect Pulse/Compute Power as rtl_no_protocols/pulsedetector_tb/Compute_Power.v. ### Working on pulsedetector_tb/PulseDetector/Detect Pulse/Local Peak/MATLAB Function as rtl_no_protocols/pulsedetector_tb/MATLAB_Function.v. ### Working on pulsedetector_tb/PulseDetector/Detect Pulse/Local Peak as rtl_no_protocols/pulsedetector_tb/Local_Peak.v. ### Working on pulsedetector_tb/PulseDetector/Detect Pulse as rtl_no_protocols/pulsedetector_tb/Detect_Pulse.v. ### Working on pulsedetector_tb/PulseDetector/Latch Peak as rtl_no_protocols/pulsedetector_tb/Latch_Peak.v. ### Working on pulsedetector_tb/PulseDetector/TDATA conversions as rtl_no_protocols/pulsedetector_tb/TDATA_conversions.v. ### Working on pulsedetector_tb/PulseDetector as rtl_no_protocols/pulsedetector_tb/PulseDetector.v. ### Code Generation for 'pulsedetector_tb' completed. ### Generating HTML files for code generation report at pulsedetector_tb_codegen_rpt.html ### Creating HDL Code Generation Check Report PulseDetector_report.html ### HDL check for 'pulsedetector_tb' complete with 0 errors, 0 warnings, and 1 messages. ### HDL code generation complete.
UVMテストベンチでDUTをオーバーライドする
インターフェースは元の C ベースのインターフェースと一致するため、次の図に示すように、UVM テストベンチで DUT 自体のみを交換する必要があります。
RTL DUTでUVMテストベンチをシミュレートする
必要なオーバーライドは overrides_RTLDUT サブディレクトリにあります。これらのオーバーライドは、RTLIPSource サブディレクトリの RTL を利用します。
この例には、Questa® をセットアップして実行するためのスクリプトが含まれています。HDL シミュレータのインストールに合わせてコマンドを調整します。
current_simulator = 'Questa';
setup_questa;次に、UVM シミュレーションに影響する環境変数をクリアします。
setenv EXTRA_UVM_SIM_ARGS setenv EXTRA_UVM_COMP_ARGS setenv UVM_TOP_MODULE
最後に、RTL ベースの DUT を使用して UVM テストベンチを実行します。
cd uvm_build/pulsedetector_tb_uvm_testbench/top setenv UVM_TOP_MODULE mw_PulseDetector_RTL_top setenv EXTRA_UVM_COMP_ARGS '-f ../../../overrides_RTLDUT/extra_comp_args.f' setenv EXTRA_UVM_SIM_ARGS '+SNR_default_inp_val=10000000' switch current_simulator case 'Questa', ! vsim -c -do run_tb_mq.do case 'Questa_gui', ! vsim -do run_tb_mq.do case 'Xcelium', ! ./run_tb_xcelium.sh case 'VCS', ! ./run_tb_vcs.sh end
Reading pref.tcl # 2022.2 # do run_tb_mq.do # -f ../../../overrides_RTLDUT/extra_comp_args.f # +SNR_default_inp_val=10000000 # QuestaSim-64 vlog 2022.2 Compiler 2022.04 Apr 25 2022 # Start time: 22:06:45 on Jun 16,2023 # vlog -timescale 1ns/1ns ../DPI_dut/PulseDetector_dpi_pkg.sv ../sequence/GenPulse_dpi_pkg.sv ../scoreboard/CheckDetection_dpi_pkg.sv ../driver/InputDriver_dpi_pkg.sv ../monitor/OutputMonitor_dpi_pkg.sv ../predictor/PulseDetectorRef_dpi_pkg.sv pulsedetector_tb_pkg.sv -f ../../../overrides_RTLDUT/extra_comp_args.f "+define+MG_SIM" # -- Compiling package PulseDetector_dpi_pkg # -- Compiling package GenPulse_dpi_pkg # -- Compiling package CheckDetection_dpi_pkg # -- Compiling package InputDriver_dpi_pkg # -- Compiling package OutputMonitor_dpi_pkg # -- Compiling package PulseDetectorRef_dpi_pkg # ** Note: (vlog-2286) pulsedetector_tb_pkg.sv(5): Using implicit +incdir+/mathworks/hub/3rdparty/R2023a/8709182/share/Questasim/Lin/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg # -- Compiling package pulsedetector_tb_pkg # -- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) # -- Importing package GenPulse_dpi_pkg # -- Importing package CheckDetection_dpi_pkg # -- Importing package PulseDetectorRef_dpi_pkg # -- Importing package InputDriver_dpi_pkg # -- Importing package OutputMonitor_dpi_pkg # -- Compiling module Create_TDATA # -- Compiling module Compute_Power # -- Compiling module MATLAB_Function # -- Compiling module Local_Peak # -- Compiling module Detect_Pulse # -- Compiling module Latch_Peak # -- Compiling module TDATA_conversions # -- Compiling module PulseDetector # -- Compiling module PulseDetectorRTL # ** Warning: ../../../overrides_RTLDUT/RTLIPSource/PulseDetectorRTL.sv(7): (vlog-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed. # -- Compiling interface mw_PulseDetector_if # -- Compiling package mw_PulseDetector_RTL_top_sv_unit # -- Importing package pulsedetector_tb_pkg # -- Compiling module mw_PulseDetector_RTL_top # # Top level modules: # mw_PulseDetector_RTL_top # End time: 22:06:45 on Jun 16,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # vsim "+SNR_default_inp_val=10000000" -L work -voptargs="+acc" -sv_lib ../DPI_dut/PulseDetector -sv_lib ../sequence/GenPulse -sv_lib ../scoreboard/CheckDetection -sv_lib ../driver/InputDriver -sv_lib ../monitor/OutputMonitor -sv_lib ../predictor/PulseDetectorRef "+UVM_TESTNAME=mw_PulseDetector_test" mw_PulseDetector_RTL_top "+define+MG_SIM" # Start time: 22:06:45 on Jun 16,2023 # ** Note: (vsim-3812) Design is being optimized... # ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility. # ** Warning: ../../../overrides_RTLDUT/RTLIPSource/PulseDetectorRTL.sv(7): (vopt-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed. # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2. # // Questa Sim-64 # // Version 2022.2 linux_x86_64 Apr 25 2022 # // # // Copyright 1991-2022 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading sv_std.std # Loading work.mw_PulseDetector_if(fast) # Loading work.OutputMonitor_dpi_pkg(fast) # Loading work.InputDriver_dpi_pkg(fast) # Loading work.PulseDetectorRef_dpi_pkg(fast) # Loading work.CheckDetection_dpi_pkg(fast) # Loading work.GenPulse_dpi_pkg(fast) # Loading mtiUvm.uvm_pkg(fast) # Loading work.pulsedetector_tb_pkg(fast) # Loading work.mw_PulseDetector_RTL_top_sv_unit(fast) # Loading mtiUvm.questa_uvm_pkg(fast) # Loading work.mw_PulseDetector_RTL_top(fast) # Loading work.mw_PulseDetector_if(fast__2) # Loading work.PulseDetectorRTL(fast) # Loading work.PulseDetector(fast) # Loading work.TDATA_conversions(fast) # Loading work.Detect_Pulse(fast) # Loading work.Compute_Power(fast) # Loading work.Local_Peak(fast) # Loading work.MATLAB_Function(fast) # Loading work.Latch_Peak(fast) # Loading work.Create_TDATA(fast) # Loading ./../DPI_dut/PulseDetector.so # Loading ./../sequence/GenPulse.so # Loading ./../scoreboard/CheckDetection.so # Loading ./../driver/InputDriver.so # Loading ./../monitor/OutputMonitor.so # Loading ./../predictor/PulseDetectorRef.so # Loading /mathworks/hub/3rdparty/R2023a/8709182/share/Questasim/Lin/uvm-1.1d/linux_x86_64/uvm_dpi.so # ---------------------------------------------------------------- # UVM-1.1d # (C) 2007-2013 Mentor Graphics Corporation # (C) 2007-2013 Cadence Design Systems, Inc. # (C) 2006-2013 Synopsys, Inc. # (C) 2011-2013 Cypress Semiconductor Corp. # ---------------------------------------------------------------- # # *********** IMPORTANT RELEASE NOTES ************ # # You are using a version of the UVM library that has been compiled # with `UVM_NO_DEPRECATED undefined. # See http://www.eda.org/svdb/view.php?id=3313 for more details. # # You are using a version of the UVM library that has been compiled # with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined. # See http://www.eda.org/svdb/view.php?id=3770 for more details. # # (Specify +UVM_NO_RELNOTES to turn off this notice) # # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3 # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct) # UVM_INFO @ 0: reporter [RNTST] Running test mw_PulseDetector_test... # ** Info: Gathering coverage for 2 Simulink verify() calls. # Time: 0 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.initVerifyInfo File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 251 # # [FrameNum= 0] No peak found in Ref or Impl. # # [FrameNum= 1] PREDICTED: Peak location=2163.000000, mag-squared=0.280 using global max # # [FrameNum= 1] ACTUAL : Peak location=2170.000000, mag-squared=0.285 using global max # # [FrameNum= 1] DIFF : Peak location=7, mag-squared=0.004 (1.551%) # # [FrameNum= 2] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max # # [FrameNum= 2] ACTUAL : Peak location=2170.000000, mag-squared=0.194 using global max # # [FrameNum= 2] DIFF : Peak location=7, mag-squared=0.006 (2.881%) # # [FrameNum= 3] PREDICTED: Peak location=2163.000000, mag-squared=0.224 using global max # # [FrameNum= 3] ACTUAL : Peak location=2170.000000, mag-squared=0.234 using global max # # [FrameNum= 3] DIFF : Peak location=7, mag-squared=0.010 (4.623%) # # [FrameNum= 4] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max # # [FrameNum= 4] ACTUAL : Peak location=2170.000000, mag-squared=0.209 using global max # # [FrameNum= 4] DIFF : Peak location=7, mag-squared=0.009 (4.346%) # # [FrameNum= 5] PREDICTED: Peak location=2163.000000, mag-squared=0.255 using global max # # [FrameNum= 5] ACTUAL : Peak location=2170.000000, mag-squared=0.257 using global max # # [FrameNum= 5] DIFF : Peak location=7, mag-squared=0.002 (0.735%) # # [FrameNum= 6] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max # # [FrameNum= 6] ACTUAL : Peak location=2170.000000, mag-squared=0.250 using global max # # [FrameNum= 6] DIFF : Peak location=7, mag-squared=0.009 (3.660%) # # [FrameNum= 7] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max # # [FrameNum= 7] ACTUAL : Peak location=2170.000000, mag-squared=0.243 using global max # # [FrameNum= 7] DIFF : Peak location=7, mag-squared=0.002 (0.790%) # # [FrameNum= 8] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max # # [FrameNum= 8] ACTUAL : Peak location=2170.000000, mag-squared=0.231 using global max # # [FrameNum= 8] DIFF : Peak location=7, mag-squared=0.007 (3.076%) # # [FrameNum= 9] PREDICTED: Peak location=2163.000000, mag-squared=0.239 using global max # # [FrameNum= 9] ACTUAL : Peak location=2170.000000, mag-squared=0.254 using global max # # [FrameNum= 9] DIFF : Peak location=7, mag-squared=0.015 (6.083%) # ** Error: pulsedetector_tb:744: # Time: 450020 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84 # ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static # Upper Bound' Failed # Time: 450020 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 347 # # [FrameNum= 10] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max # # [FrameNum= 10] ACTUAL : Peak location=2170.000000, mag-squared=0.230 using global max # # [FrameNum= 10] DIFF : Peak location=7, mag-squared=0.005 (2.242%) # # [FrameNum= 11] PREDICTED: Peak location=2163.000000, mag-squared=0.207 using global max # # [FrameNum= 11] ACTUAL : Peak location=2170.000000, mag-squared=0.221 using global max # # [FrameNum= 11] DIFF : Peak location=7, mag-squared=0.014 (6.697%) # ** Error: pulsedetector_tb:744: # Time: 550020 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84 # ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static # Upper Bound' Failed # Time: 550020 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 347 # # [FrameNum= 12] PREDICTED: Peak location=2163.000000, mag-squared=0.265 using global max # # [FrameNum= 12] ACTUAL : Peak location=2170.000000, mag-squared=0.260 using global max # # [FrameNum= 12] DIFF : Peak location=7, mag-squared=0.005 (2.014%) # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 650000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # ** Info: Instance coverage for verify 'pulsedetector_tb:757', coverpoint 'pass_cp': metric=100.00, at_least= 1 ( COVERED) # Time: 650 us Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 369 # ** Info: Instance coverage for verify 'pulsedetector_tb:744', coverpoint 'pass_cp': metric=100.00, at_least= 1 ( COVERED) # Time: 650 us Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 369 # ** Info: Overall coverage for CheckDetection_dpi_verify_calls: metric=100.00 ( COVERED) # Time: 650 us Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 376 # # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 4 # UVM_WARNING : 0 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [Questa UVM] 2 # [RNTST] 1 # [TEST_DONE] 1 # ** Note: $finish : /mathworks/hub/3rdparty/R2023a/8709182/share/Questasim/Lin/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) # Time: 650 us Iteration: 61 Instance: /mw_PulseDetector_RTL_top # End time: 22:07:30 on Jun 16,2023, Elapsed time: 0:00:45 # Errors: 4, Warnings: 2
cd ../../..C ベースの DUT を AXI ベースの RTL DUT に置き換える
Simulink の DUT はパルス検出器の機能動作を表し、HDL IP コアに典型的なハードウェア プロトコル インターフェイスは使用しません。検証ワークフローの次のステップでは、AXI ベースのプロトコルを使用する HDL 実装を、生成された同じ UVM テストベンチに統合します。
ポートをAXIインターフェースにマッピングする
この RTL DUT では、次に示すように、coeff ポートはプロセッサ インターフェイス AXI4-Lite にマップされ、data_in ポートは AXI4-Stream スレーブ インターフェイスにマップされ、data_out ポートは AXI4-Stream マスター インターフェイスにマップされます。
この RTL を手動で記述することも、IP コア生成ワークフロー (HDL Coder が必要) を使用して作成することもできます。
AXIベースのRTL DUTを生成する
RTL 実装は overrides_AXIDUT/AXIIPSource にあるこの例に含まれているため、HDL Coder ライセンスは必要ありません。
HDL Coder をお持ちの場合は、信号を AXI インターフェイスにマップし、指定されたハードウェア プロトコルを使用して RTL IP コアを生成できます。
生成をスクリプト化するために、HDL Coder 設定を pulsedetector_genaxidut にエクスポートしました。
この例には、Vivado® を実行するための MathWorks 固有のセットアップが含まれています。インストールに合わせてコマンドを調整します。
setup_vivado
次に、HDL Coder を使用して AXI ベースの RTL DUT を生成するスクリプトを実行します。
pulsedetector_genaxidut
### Workflow begin. ### Loading settings from model. ### Generating HDL for 'pulsedetector_tb/PulseDetector'. ### Using the config set for model pulsedetector_tb for HDL code generation parameters. ### Running HDL checks on the model 'pulsedetector_tb'. ### Begin compilation of the model 'pulsedetector_tb'... ### Begin compilation of the model 'pulsedetector_tb'...
Warning: AXI4-Stream Protocol requires TDATA port width to be integer number of bytes. In the generated HDL code, the bitwidth of the TDATA port of the interface "AXI4-Stream Master" will be 72 bits.
### ++++++++++++++ Task Generate RTL Code and IP Core ++++++++++++++
### Working on the model 'pulsedetector_tb'...
### Starting Verilog code generation process for filter: filter
### 'LUTMapToRAM' is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware. To disable pipeline insertion for mapping lookup tables to RAM, please set the option to 'Off'.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 8 cycles.
### Output port 2: 8 cycles.
### Working on... GenerateModel
### Begin model generation 'gm_pulsedetector_tb' ....
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Begin Verilog Code Generation for 'pulsedetector_tb'.
### Working on pulsedetector_tb/PulseDetector/Create TDATA as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_Create_TDATA.v.
### Working on pulsedetector_tb/PulseDetector/Detect Pulse/Compute Power as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_Compute_Power.v.
### Working on pulsedetector_tb/PulseDetector/Detect Pulse/Local Peak/MATLAB Function as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_MATLAB_Function.v.
### Working on pulsedetector_tb/PulseDetector/Detect Pulse/Local Peak as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_Local_Peak.v.
### Working on pulsedetector_tb/PulseDetector/Detect Pulse as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_Detect_Pulse.v.
### Working on pulsedetector_tb/PulseDetector/Latch Peak as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_Latch_Peak.v.
### Working on pulsedetector_tb/PulseDetector/TDATA conversions as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_TDATA_conversions.v.
### Working on pulsedetector_tb/PulseDetector as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_src_PulseDetector.v.
### Code Generation for 'pulsedetector_tb' completed.
### Generating HTML files for code generation report at pulsedetector_tb_codegen_rpt.html
### Creating HDL Code Generation Check Report PulseDetectorAXI_ip_src_PulseDetector_report.html
### HDL check for 'pulsedetector_tb' complete with 0 errors, 0 warnings, and 1 messages.
### HDL code generation complete.
### Begin IP core top level wrapper code generation.
### Begin Verilog Code Generation for 'pulsedetector_tb'.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_reset_sync as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_reset_sync.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_dut as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_dut.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_master/PulseDetectorAXI_ip_fifo_data_OUT/PulseDetectorAXI_ip_fifo_data_OUT_classic/PulseDetectorAXI_ip_SimpleDualPortRAM_generic as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_SimpleDualPortRAM_generic.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_master/PulseDetectorAXI_ip_fifo_data_OUT as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_fifo_data_OUT.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_master/PulseDetectorAXI_ip_fifo_TLAST_OUT/PulseDetectorAXI_ip_fifo_TLAST_OUT_classic/PulseDetectorAXI_ip_SimpleDualPortRAM_singlebit as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_SimpleDualPortRAM_singlebit.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_master/PulseDetectorAXI_ip_fifo_TLAST_OUT as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_fifo_TLAST_OUT.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_master as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_axi4_stream_master.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_slave/PulseDetectorAXI_ip_fifo_data as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_fifo_data.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi4_stream_slave as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_axi4_stream_slave.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi_lite/PulseDetectorAXI_ip_addr_decoder as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_addr_decoder.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi_lite/PulseDetectorAXI_ip_axi_lite_module as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_axi_lite_module.v.
### Working on PulseDetectorAXI_ip/PulseDetectorAXI_ip_axi_lite as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip_axi_lite.v.
### Working on PulseDetectorAXI_ip as rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/PulseDetectorAXI_ip.v.
### Code Generation for 'pulsedetector_tb' completed.
### HDL code generation complete.
### Begin IP core packaging.
### Generating IP core report pulsedetector_tb_ip_core_report.html
### Generated logfile: rtl_with_axi_protocols/hdlsrc/pulsedetector_tb/workflow_task_VivadoIPPackager.log
### Task "Vivado IP Packager" successful.
###
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2521.500 ; gain = 0.023 ; free physical = 8787 ; free virtual = 35671
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/merickso/Documents/MATLAB/ExampleManager/merickso.Bdoc23b.j2301974.r23bI10_ex2_uvm/hdlverifier-ex70605950/pulsedetector_proj/rtl_with_axi_protocols/ipcore'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/merickso/Documents/MATLAB/ExampleManager/merickso.Bdoc23b.j2301974.r23bI10_ex2_uvm/hdlverifier-ex70605950/pulsedetector_proj/rtl_with_axi_protocols/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/merickso/Documents/MATLAB/ExampleManager/merickso.Bdoc23b.j2301974.r23bI10_ex2_uvm/hdlverifier-ex70605950/pulsedetector_proj/rtl_with_axi_protocols/ipcore/PulseDetectorAXI_ip_v1_0/prj_ip'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/mathworks/hub/share/apps/HDLTools/Vivado/2022.1-mw-0/Lin/Vivado/2022.1/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Stream_Master' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Stream_Slave' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'.
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'.
INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'.
WARNING: [IP_Flow 19-3158] Bus Interface 'AXI4_Stream_Master': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'AXI4_Stream_Slave': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-5661] Bus Interface 'IPCORE_CLK' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Create_TDATA.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Create_TDATA.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Compute_Power.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Compute_Power.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_MATLAB_Function.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_MATLAB_Function.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Local_Peak.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Local_Peak.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Detect_Pulse.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Detect_Pulse.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Latch_Peak.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_Latch_Peak.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_TDATA_conversions.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_TDATA_conversions.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_PulseDetector.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_src_PulseDetector.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_reset_sync.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_reset_sync.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_dut.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_dut.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_SimpleDualPortRAM_generic.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_SimpleDualPortRAM_generic.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_fifo_data_OUT.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_fifo_data_OUT.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_SimpleDualPortRAM_singlebit.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_SimpleDualPortRAM_singlebit.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_fifo_TLAST_OUT.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_fifo_TLAST_OUT.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi4_stream_master.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi4_stream_master.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_fifo_data.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_fifo_data.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi4_stream_slave.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi4_stream_slave.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi_lite.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip_axi_lite.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "hdl/PulseDetectorAXI_ip.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
INFO: [Common 17-206] Exiting Vivado at Fri Jun 16 22:15:48 2023...
Elapsed time is 38.7377 seconds.
### Workflow complete.
これにより、結果の HDL IP ファイルが rtl_with_axi_protocols/hdlsrc/pulsedetector_tb に配置されます。
必要なUVMコンポーネントを上書きする
元の DUT を置き換える UVM ファイルは overrides_AXIDUT にあります。元の uvmbuild 呼び出しから生成されたファイルを変更する必要はありません。
mw_PulseDetector_AXIRTL_if.sv:メイン DUT インターフェース クラスを再定義します。元のインターフェース定義と比較します。
mw_PulseDetector_AXIRTL_driver.sv:DUT インターフェイスの AXI プロトコルに従って入力トランザクションを駆動します。元のドライバーと比較します。
mw_PulseDetector_AXIRTL_monitor/monitor_input.sv:ストリーミングされた AXI データを受信し、以前と同じトランザクション タイプに変換します。元のモニター定義と比較します。
mw_PulseDetector_AXIRTL_top.sv:AXI RTL DUT をインスタンス化し、メインの UVM パッケージを含めます。元のトップ定義と比較します。
RTL DUT を使用するには、ピンクで強調表示されている UVM テストベンチの一部を置き換える必要があります。
AXI RTL DUT で UVM テストベンチをシミュレートする
新しい RTL DUT を使用してテストベンチを実行し、UVM 実行が Simulink 実行と一致することを確認します。シーケンスは SNR 入力ポートでパラメータ化されるため、UVM ではデフォルト値は 0.0 になります。シミュレーション実行を適切に比較するには、デフォルト値を 2.0 (ビット値は 0b10_000000) に変更して、Simulink と一致させる必要があります。これは、環境変数を介してスクリプトに渡す plusarg を介して実行できます。
コンパイルする新しい RTL ファイルが多数あり、トップレベルの設計ユニットをオーバーライドする必要があります。これらの更新は環境変数を通じてスクリプトに渡されます。
cd uvm_build/pulsedetector_tb_uvm_testbench/top setenv UVM_TOP_MODULE mw_PulseDetector_AXIRTL_top setenv EXTRA_UVM_COMP_ARGS '-f ../../../overrides_AXIDUT/extra_comp_args.f' setenv EXTRA_UVM_SIM_ARGS '+SNR_default_inp_val=10000000 +UVM_TESTNAME=mw_PulseDetector_AXIRTL_test' switch current_simulator case 'Questa', ! vsim -c -do run_tb_mq.do case 'Questa_gui', ! vsim -do run_tb_mq.do case 'Xcelium', ! ./run_tb_xcelium.sh case 'VCS', ! ./run_tb_vcs.sh end
Reading pref.tcl # 2022.2 # do run_tb_mq.do # -f ../../../overrides_AXIDUT/extra_comp_args.f # +SNR_default_inp_val=10000000 +UVM_TESTNAME=mw_PulseDetector_AXIRTL_test # ** Warning: (vlib-34) Library already exists at "work". # Errors: 0, Warnings: 1 # QuestaSim-64 vlog 2022.2 Compiler 2022.04 Apr 25 2022 # Start time: 22:15:49 on Jun 16,2023 # vlog -timescale 1ns/1ns ../DPI_dut/PulseDetector_dpi_pkg.sv ../sequence/GenPulse_dpi_pkg.sv ../scoreboard/CheckDetection_dpi_pkg.sv ../driver/InputDriver_dpi_pkg.sv ../monitor/OutputMonitor_dpi_pkg.sv ../predictor/PulseDetectorRef_dpi_pkg.sv pulsedetector_tb_pkg.sv -f ../../../overrides_AXIDUT/extra_comp_args.f "+define+MG_SIM" # -- Compiling package PulseDetector_dpi_pkg # -- Compiling package GenPulse_dpi_pkg # -- Compiling package CheckDetection_dpi_pkg # -- Compiling package InputDriver_dpi_pkg # -- Compiling package OutputMonitor_dpi_pkg # -- Compiling package PulseDetectorRef_dpi_pkg # ** Note: (vlog-2286) pulsedetector_tb_pkg.sv(5): Using implicit +incdir+/mathworks/hub/3rdparty/R2023a/8709182/share/Questasim/Lin/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg # -- Compiling package pulsedetector_tb_pkg # -- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) # -- Importing package GenPulse_dpi_pkg # -- Importing package CheckDetection_dpi_pkg # -- Importing package PulseDetectorRef_dpi_pkg # -- Importing package InputDriver_dpi_pkg # -- Importing package OutputMonitor_dpi_pkg # -- Compiling module PulseDetectorAXI_ip_src_Create_TDATA # -- Compiling module PulseDetectorAXI_ip_src_Compute_Power # -- Compiling module PulseDetectorAXI_ip_src_MATLAB_Function # -- Compiling module PulseDetectorAXI_ip_src_Local_Peak # -- Compiling module PulseDetectorAXI_ip_src_Detect_Pulse # -- Compiling module PulseDetectorAXI_ip_src_Latch_Peak # -- Compiling module PulseDetectorAXI_ip_src_TDATA_conversions # -- Compiling module PulseDetectorAXI_ip_src_PulseDetector # -- Compiling module PulseDetectorAXI_ip_reset_sync # -- Compiling module PulseDetectorAXI_ip_dut # -- Compiling module PulseDetectorAXI_ip_SimpleDualPortRAM_generic # -- Compiling module PulseDetectorAXI_ip_fifo_data_OUT # -- Compiling module PulseDetectorAXI_ip_SimpleDualPortRAM_singlebit # -- Compiling module PulseDetectorAXI_ip_fifo_TLAST_OUT # -- Compiling module PulseDetectorAXI_ip_axi4_stream_master # -- Compiling module PulseDetectorAXI_ip_fifo_data # -- Compiling module PulseDetectorAXI_ip_axi4_stream_slave # -- Compiling module PulseDetectorAXI_ip_addr_decoder # -- Compiling module PulseDetectorAXI_ip_axi_lite_module # -- Compiling module PulseDetectorAXI_ip_axi_lite # -- Compiling module PulseDetectorAXI_ip # -- Compiling package pulsedetector_tb_extension_pkg # -- Importing package pulsedetector_tb_pkg # ** Warning: ** while parsing file included at ../../../overrides_AXIDUT/mw_PulseDetector_AXIRTL_top.sv(4) # ** at ../DPI_dut/PulseDetector_dpi.sv(15): (vlog-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed. # -- Compiling package mw_PulseDetector_AXIRTL_top_sv_unit # -- Importing package PulseDetector_dpi_pkg # -- Importing package pulsedetector_tb_extension_pkg # -- Compiling module PulseDetector_dpi # ** Warning: ../DPI_dut/PulseDetector_dpi.sv(15): (vlog-13314) Defaulting port 'coeff_in' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed. # -- Compiling interface mw_PulseDetector_AXIRTL_if # -- Compiling interface mw_PulseDetector_if # -- Compiling module mw_PulseDetector_AXIRTL_top # # Top level modules: # PulseDetector_dpi # mw_PulseDetector_AXIRTL_top # End time: 22:15:50 on Jun 16,2023, Elapsed time: 0:00:01 # Errors: 0, Warnings: 2 # vsim "+SNR_default_inp_val=10000000" "+UVM_TESTNAME=mw_PulseDetector_AXIRTL_test" -L work -voptargs="+acc" -sv_lib ../DPI_dut/PulseDetector -sv_lib ../sequence/GenPulse -sv_lib ../scoreboard/CheckDetection -sv_lib ../driver/InputDriver -sv_lib ../monitor/OutputMonitor -sv_lib ../predictor/PulseDetectorRef "+UVM_TESTNAME=mw_PulseDetector_test" mw_PulseDetector_AXIRTL_top "+define+MG_SIM" # Start time: 22:15:50 on Jun 16,2023 # ** Note: (vsim-3812) Design is being optimized... # ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility. # ** Note: (vopt-143) Recognized 2 FSMs in module "PulseDetectorAXI_ip_axi_lite_module(fast)". # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1. # // Questa Sim-64 # // Version 2022.2 linux_x86_64 Apr 25 2022 # // # // Copyright 1991-2022 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading sv_std.std # Loading work.mw_PulseDetector_AXIRTL_if(fast) # Loading work.mw_PulseDetector_if(fast) # Loading work.OutputMonitor_dpi_pkg(fast) # Loading work.InputDriver_dpi_pkg(fast) # Loading work.PulseDetectorRef_dpi_pkg(fast) # Loading work.CheckDetection_dpi_pkg(fast) # Loading work.GenPulse_dpi_pkg(fast) # Loading mtiUvm.uvm_pkg(fast) # Loading work.pulsedetector_tb_pkg(fast) # Loading work.pulsedetector_tb_extension_pkg(fast) # Loading work.PulseDetector_dpi_pkg(fast) # Loading work.mw_PulseDetector_AXIRTL_top_sv_unit(fast) # Loading mtiUvm.questa_uvm_pkg(fast) # Loading work.mw_PulseDetector_AXIRTL_top(fast) # Loading work.mw_PulseDetector_if(fast__2) # Loading work.mw_PulseDetector_AXIRTL_if(fast__2) # Loading work.PulseDetectorAXI_ip(fast) # Loading work.PulseDetectorAXI_ip_reset_sync(fast) # Loading work.PulseDetectorAXI_ip_axi_lite(fast) # Loading work.PulseDetectorAXI_ip_addr_decoder(fast) # Loading work.PulseDetectorAXI_ip_axi_lite_module(fast) # Loading work.PulseDetectorAXI_ip_axi4_stream_slave(fast) # Loading work.PulseDetectorAXI_ip_fifo_data(fast) # Loading work.PulseDetectorAXI_ip_SimpleDualPortRAM_generic(fast) # Loading work.PulseDetectorAXI_ip_dut(fast) # Loading work.PulseDetectorAXI_ip_src_PulseDetector(fast) # Loading work.PulseDetectorAXI_ip_src_TDATA_conversions(fast) # Loading work.PulseDetectorAXI_ip_src_Detect_Pulse(fast) # Loading work.PulseDetectorAXI_ip_src_Compute_Power(fast) # Loading work.PulseDetectorAXI_ip_src_Local_Peak(fast) # Loading work.PulseDetectorAXI_ip_src_MATLAB_Function(fast) # Loading work.PulseDetectorAXI_ip_src_Latch_Peak(fast) # Loading work.PulseDetectorAXI_ip_src_Create_TDATA(fast) # Loading work.PulseDetectorAXI_ip_axi4_stream_master(fast) # Loading work.PulseDetectorAXI_ip_fifo_data_OUT(fast) # Loading work.PulseDetectorAXI_ip_SimpleDualPortRAM_generic(fast__1) # Loading work.PulseDetectorAXI_ip_fifo_TLAST_OUT(fast) # Loading work.PulseDetectorAXI_ip_SimpleDualPortRAM_singlebit(fast) # Loading ./../DPI_dut/PulseDetector.so # Loading ./../sequence/GenPulse.so # Loading ./../scoreboard/CheckDetection.so # Loading ./../driver/InputDriver.so # Loading ./../monitor/OutputMonitor.so # Loading ./../predictor/PulseDetectorRef.so # Loading /mathworks/hub/3rdparty/R2023a/8709182/share/Questasim/Lin/uvm-1.1d/linux_x86_64/uvm_dpi.so # ---------------------------------------------------------------- # UVM-1.1d # (C) 2007-2013 Mentor Graphics Corporation # (C) 2007-2013 Cadence Design Systems, Inc. # (C) 2006-2013 Synopsys, Inc. # (C) 2011-2013 Cypress Semiconductor Corp. # ---------------------------------------------------------------- # # *********** IMPORTANT RELEASE NOTES ************ # # You are using a version of the UVM library that has been compiled # with `UVM_NO_DEPRECATED undefined. # See http://www.eda.org/svdb/view.php?id=3313 for more details. # # You are using a version of the UVM library that has been compiled # with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined. # See http://www.eda.org/svdb/view.php?id=3770 for more details. # # (Specify +UVM_NO_RELNOTES to turn off this notice) # # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3 # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct) # UVM_WARNING @ 0: reporter [MULTTST] Multiple (2) +UVM_TESTNAME arguments provided on the command line. 'mw_PulseDetector_AXIRTL_test' will be used. Provided list: mw_PulseDetector_AXIRTL_test, mw_PulseDetector_test. # UVM_INFO @ 0: reporter [RNTST] Running test mw_PulseDetector_AXIRTL_test... # UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology: # ------------------------------------------------------------------------------------------------------------- # Name Type Size Value # ------------------------------------------------------------------------------------------------------------- # uvm_test_top mw_PulseDetector_AXIRTL_test - @477 # env mw_PulseDetector_environment - @484 # PulseDetector_agent mw_PulseDetector_AXIRTL_agent - @500 # ap uvm_analysis_port - @631 # ap_input_pred uvm_analysis_port - @639 # drv mw_PulseDetector_AXIRTL_driver - @647 # rsp_port uvm_analysis_port - @662 # seq_item_port uvm_seq_item_pull_port - @654 # mon mw_PulseDetector_AXIRTL_monitor - @670 # mw_PulseDetector_monitor_analysis_port uvm_analysis_port - @677 # mon_input mw_PulseDetector_AXIRTL_monitor_input - @685 # mw_PulseDetector_monitor_input_analysis_port_pred uvm_analysis_port - @692 # sqr mw_PulseDetector_sequencer - @522 # rsp_export uvm_analysis_export - @529 # seq_item_export uvm_seq_item_pull_imp - @623 # arbitration_queue array 0 - # lock_queue array 0 - # num_last_reqs integral 32 'd1 # num_last_rsps integral 32 'd1 # PulseDetector_predictor mw_PulseDetector_predictor - @514 # aexp uvm_analysis_export - @709 # ap uvm_analysis_port - @764 # mw_PulseDetector_predictor_fifo uvm_tlm_analysis_fifo #(T) - @717 # analysis_export uvm_analysis_imp - @756 # get_ap uvm_analysis_port - @748 # get_peek_export uvm_get_peek_imp - @732 # put_ap uvm_analysis_port - @740 # put_export uvm_put_imp - @724 # PulseDetector_scoreboard mw_PulseDetector_scoreboard - @507 # mw_PulseDetector_agent_fifo uvm_tlm_analysis_fifo #(T) - @796 # analysis_export uvm_analysis_imp - @835 # get_ap uvm_analysis_port - @827 # get_peek_export uvm_get_peek_imp - @811 # put_ap uvm_analysis_port - @819 # put_export uvm_put_imp - @803 # mw_PulseDetector_agent_fifo_input_pred uvm_tlm_analysis_fifo #(T) - @843 # analysis_export uvm_analysis_imp - @882 # get_ap uvm_analysis_port - @874 # get_peek_export uvm_get_peek_imp - @858 # put_ap uvm_analysis_port - @866 # put_export uvm_put_imp - @850 # mw_PulseDetector_agent_imp uvm_analysis_export - @780 # mw_PulseDetector_agent_imp_input_pred uvm_analysis_export - @788 # ------------------------------------------------------------------------------------------------------------- # # ** Info: Gathering coverage for 2 Simulink verify() calls. # Time: 0 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.initVerifyInfo File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 251 # # [FrameNum= 0] Peak found in Impl but not in Ref. # ** Error: pulsedetector_tb:744: # Time: 54885 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84 # ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static # Upper Bound' Failed # Time: 54885 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 347 # # [FrameNum= 1] PREDICTED: Peak location=2163.000000, mag-squared=0.280 using global max # # [FrameNum= 1] ACTUAL : Peak location=2169.000000, mag-squared=0.285 using global max # # [FrameNum= 1] DIFF : Peak location=6, mag-squared=0.004 (1.551%) # # [FrameNum= 2] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max # # [FrameNum= 2] ACTUAL : Peak location=2168.000000, mag-squared=0.194 using global max # # [FrameNum= 2] DIFF : Peak location=5, mag-squared=0.006 (2.881%) # # [FrameNum= 3] PREDICTED: Peak location=2163.000000, mag-squared=0.224 using global max # # [FrameNum= 3] ACTUAL : Peak location=2167.000000, mag-squared=0.234 using global max # # [FrameNum= 3] DIFF : Peak location=4, mag-squared=0.010 (4.623%) # # [FrameNum= 4] PREDICTED: Peak location=2163.000000, mag-squared=0.200 using global max # # [FrameNum= 4] ACTUAL : Peak location=2166.000000, mag-squared=0.209 using global max # # [FrameNum= 4] DIFF : Peak location=3, mag-squared=0.009 (4.346%) # # [FrameNum= 5] PREDICTED: Peak location=2163.000000, mag-squared=0.255 using global max # # [FrameNum= 5] ACTUAL : Peak location=2165.000000, mag-squared=0.257 using global max # # [FrameNum= 5] DIFF : Peak location=2, mag-squared=0.002 (0.735%) # # [FrameNum= 6] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max # # [FrameNum= 6] ACTUAL : Peak location=2164.000000, mag-squared=0.250 using global max # # [FrameNum= 6] DIFF : Peak location=1, mag-squared=0.009 (3.660%) # # [FrameNum= 7] PREDICTED: Peak location=2163.000000, mag-squared=0.241 using global max # # [FrameNum= 7] ACTUAL : Peak location=2163.000000, mag-squared=0.243 using global max # # [FrameNum= 7] DIFF : Peak location=0, mag-squared=0.002 (0.790%) # # [FrameNum= 8] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max # # [FrameNum= 8] ACTUAL : Peak location=2162.000000, mag-squared=0.231 using global max # # [FrameNum= 8] DIFF : Peak location=1, mag-squared=0.007 (3.076%) # # [FrameNum= 9] PREDICTED: Peak location=2163.000000, mag-squared=0.239 using global max # # [FrameNum= 9] ACTUAL : Peak location=2161.000000, mag-squared=0.254 using global max # # [FrameNum= 9] DIFF : Peak location=2, mag-squared=0.015 (6.083%) # ** Error: pulsedetector_tb:744: # Time: 548715 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84 # ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static # Upper Bound' Failed # Time: 548715 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 347 # # [FrameNum= 10] PREDICTED: Peak location=2163.000000, mag-squared=0.225 using global max # # [FrameNum= 10] ACTUAL : Peak location=2160.000000, mag-squared=0.230 using global max # # [FrameNum= 10] DIFF : Peak location=3, mag-squared=0.005 (2.242%) # # [FrameNum= 11] PREDICTED: Peak location=2163.000000, mag-squared=0.207 using global max # # [FrameNum= 11] ACTUAL : Peak location=2159.000000, mag-squared=0.221 using global max # # [FrameNum= 11] DIFF : Peak location=4, mag-squared=0.014 (6.697%) # ** Error: pulsedetector_tb:744: # Time: 658455 ns Scope: pulsedetector_tb_pkg.mw_PulseDetector_scoreboard.run_phase File: ../scoreboard/mw_PulseDetector_scoreboard.sv Line: 84 # ** Error: pulsedetector_tb:744: At step 'inferred verify call' verify id 'CheckDetection/CheckDetection/Check Static # Upper Bound' Failed # Time: 658455 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.checkVerifyStatus File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 347 # # [FrameNum= 12] PREDICTED: Peak location=2163.000000, mag-squared=0.265 using global max # # [FrameNum= 12] ACTUAL : Peak location=2158.000000, mag-squared=0.260 using global max # # [FrameNum= 12] DIFF : Peak location=5, mag-squared=0.005 (2.014%) # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 713385: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # ** Info: Instance coverage for verify 'pulsedetector_tb:757', coverpoint 'pass_cp': metric=100.00, at_least= 1 ( COVERED) # Time: 713385 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 369 # ** Info: Instance coverage for verify 'pulsedetector_tb:744', coverpoint 'pass_cp': metric=100.00, at_least= 1 ( COVERED) # Time: 713385 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 369 # ** Info: Overall coverage for CheckDetection_dpi_verify_calls: metric=100.00 ( COVERED) # Time: 713385 ns Scope: CheckDetection_dpi_pkg.VerifyInterfaceT.reportVerifyCoverage File: ../scoreboard/CheckDetection_dpi_pkg.sv Line: 376 # # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 5 # UVM_WARNING : 1 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [MULTTST] 1 # [Questa UVM] 2 # [RNTST] 1 # [TEST_DONE] 1 # [UVMTOP] 1 # ** Note: $finish : /mathworks/hub/3rdparty/R2023a/8709182/share/Questasim/Lin/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) # Time: 713385 ns Iteration: 61 Instance: /mw_PulseDetector_AXIRTL_top # End time: 22:16:23 on Jun 16,2023, Elapsed time: 0:00:33 # Errors: 6, Warnings: 1
cd ../../..以下に波形を示し、設計を実行するためのさまざまなタイミングを示します。常に有効なデータの安定したストリームの代わりに、5000 個の信号サンプルの各フレームに対して、最初に 64 個の係数がプロセッサ インターフェイスを介してプログラムされ、次に 5000 個のサンプルがストリーミングされます。
この最初の波形は、1 つのフレームの開始点にあるカーソルと、次のフレームの開始点にある別のカーソルを示しています。
次の波形は、プロセッサ インターフェイスを介して次の係数セットが送信されているときに、カーソルが TLAST の 1 つのフレームの終わりにあり、もう 1 つのカーソルが次のフレームの先頭にある詳細ビューを示しています。
結論と次のステップ
この例では、Simulink で開発された設計とテストベンチを使用して、完全に実行可能な UVM テストベンチを生成する方法を示しました。uvmbuild コマンドは、主要なコンポーネントの生成、コンパイル、および UVM フレームワークへの統合を自動化します。
HDL 検証エンジニアは、Simulink から全体的なカバレッジを確認し、独自のネイティブ UVM シーケンス ライブラリを使用してカバレッジを拡張できます。
また、元のシーケンス ジェネレーターと応答チェッカーを変更することなく、Simulink の動作設計を、AXI4 などのハードウェア プロトコルでラップされた RTL 設計に置き換えることもできます。
参考
uvmbuild | makehdl (HDL Coder)
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