Allow clock-rate pipelining of DUT output ports

Produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate

Model Configuration Pane: Optimization / Pipelining

Description

Produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate.

Dependencies

When you specify this parameter, make sure that you select the Clock-rate pipelining check box.

Settings

On (default) | Off

On

Produce the DUT outputs as soon as possible at the clock rate.

Off

Produce the DUT outputs at the data rate.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the ClockRatePipelineOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('sfir_fixed/symmetric_fir', ... 
          'ClockRatePipelineOutputPorts','on')

• When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

  hdlset_param('sfir_fixed','ClockRatePipelineOutputPorts','on')
  makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: ClockRatePipelineOutputPorts

Type: character vector

Value: 'on' | 'off'

Default: 'off'

Version History

Introduced in R2015a