Kiran Kintali
Last seen: Today
MathWorks
349 2011 年以降の合計貢献数Professional Interests: Signal Processing, FPGAs and ESL Design
Kiran Kintali's バッジ
Your submissions were downloaded 100 or more times in a month
Awarded to Kiran Kintali on 01 Apr 2021
Answer 50 questions that were unanswered for more than 30 days
Awarded to Kiran Kintali on 01 Nov 2020
Contribute at least one answer each month for 12 consecutive months
Awarded to Kiran Kintali on 02 Jul 2020
Your submissions received 10 five star ratings
Awarded to Kiran Kintali on 21 Jun 2020
Publish your first comment or rating
Awarded to Kiran Kintali on 09 Oct 2019
Publish your first submission
Awarded to Kiran Kintali on 09 Oct 2019
20 of your answers have been accepted
Awarded to Kiran Kintali on 26 Sep 2018
Provide your first answer ever to someone else's question
Awarded to Kiran Kintali on 20 Jul 2017
回答済み
How to link the fixed point tool result back to HDL coder inside filter design tool?
You can export the filter from FDATool to Simulink via File->Export to Simulink Model, click the “Realize Model” button and run ...
How to link the fixed point tool result back to HDL coder inside filter design tool?
You can export the filter from FDATool to Simulink via File->Export to Simulink Model, click the “Realize Model” button and run ...
6日 前 | 0
回答済み
Error when generating test bench
Need dut.m and testbench.m and a project file (with data type settings, HDL settings) to debug such floating point to fixed poit...
Error when generating test bench
Need dut.m and testbench.m and a project file (with data type settings, HDL settings) to debug such floating point to fixed poit...
6日 前 | 0
回答済み
HDL Reciprocal speed limitation?
For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-poi...
HDL Reciprocal speed limitation?
For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-poi...
6日 前 | 0
回答済み
HDL Coder RAM generation for an array
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB® code to RAM. Without this optimization,...
HDL Coder RAM generation for an array
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB® code to RAM. Without this optimization,...
6日 前 | 0
回答済み
Error: HDL Verification --> Verify with HDL TestBench
This error is not reproducible in R2020a/R2020b/R2021b versions. Please attach design.m and testbench.m and the project with set...
Error: HDL Verification --> Verify with HDL TestBench
This error is not reproducible in R2020a/R2020b/R2021b versions. Please attach design.m and testbench.m and the project with set...
6日 前 | 0
回答済み
How to do an HDL Coder design with asynchronous clocks and do resource sharing?
There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Refe...
How to do an HDL Coder design with asynchronous clocks and do resource sharing?
There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Refe...
7日 前 | 0
回答済み
Error Found unsupported dimensions on matrix type at output port:
Attached are few examples of how to code matrix multiply in HDL Coder.
Error Found unsupported dimensions on matrix type at output port:
Attached are few examples of how to code matrix multiply in HDL Coder.
7日 前 | 0
回答済み
The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.
The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.
13日 前 | 0
回答済み
Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitabl...
Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitabl...
17日 前 | 0
回答済み
Getting error while generating hdl code
What version of MATLAB and HDL Coder are you currently using? Can you share output of 'ver' command? I wonder if you have an b...
Getting error while generating hdl code
What version of MATLAB and HDL Coder are you currently using? Can you share output of 'ver' command? I wonder if you have an b...
21日 前 | 1
回答済み
Implementation of a SystemVerilog block in a Simulink simulation
https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html Consider using cosimulation feature. You can also integr...
Implementation of a SystemVerilog block in a Simulink simulation
https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html Consider using cosimulation feature. You can also integr...
約1ヶ月 前 | 0
回答済み
Can SimEvent library components be used with HDL Coder?
HDL Code Generation is supported for SimEvents Blocks. Consider sharing your usecases by reaching out to support@mathworks.com...
Can SimEvent library components be used with HDL Coder?
HDL Code Generation is supported for SimEvents Blocks. Consider sharing your usecases by reaching out to support@mathworks.com...
約1ヶ月 前 | 0
回答済み
Trenz Electronic TE0820 support in HDL coder toolbox
>> I want to create the algorithm as Simulink models and execute these models in Simulink external mode for debuging and data ga...
Trenz Electronic TE0820 support in HDL coder toolbox
>> I want to create the algorithm as Simulink models and execute these models in Simulink external mode for debuging and data ga...
約2ヶ月 前 | 0
| 採用済み
回答済み
HDL Code Generation Block Support
HDL Coder specific library in Simulink provides few HDL friendly blocks like RAM, FIFO etc., that are suited for HDL code genera...
HDL Code Generation Block Support
HDL Coder specific library in Simulink provides few HDL friendly blocks like RAM, FIFO etc., that are suited for HDL code genera...
約2ヶ月 前 | 0
回答済み
Passing HDL parameters through models
This may not yet be supported in HDL block dialogs. Please reach out to support@mathworks.com with your request and usecase mode...
Passing HDL parameters through models
This may not yet be supported in HDL block dialogs. Please reach out to support@mathworks.com with your request and usecase mode...
2ヶ月 前 | 0
回答済み
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
See the attached file with examples on some of the coding styles. Some of the examples contain FFT variations in MATLAB suitabl...
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
See the attached file with examples on some of the coding styles. Some of the examples contain FFT variations in MATLAB suitabl...
2ヶ月 前 | 0
回答済み
VHDL Coder Error: variable-size matrix type is not supported for VHDL code generation
Can you check MALTAB to HDL documentation for examples on how to break the design into dut and testbench files? feel free to att...
VHDL Coder Error: variable-size matrix type is not supported for VHDL code generation
Can you check MALTAB to HDL documentation for examples on how to break the design into dut and testbench files? feel free to att...
2ヶ月 前 | 1
回答済み
How to convert this simulink model to VHDL ?
Attached a sample model. Please feel free to share your models. What is the exact frequency and is it a constant or variable wi...
How to convert this simulink model to VHDL ?
Attached a sample model. Please feel free to share your models. What is the exact frequency and is it a constant or variable wi...
2ヶ月 前 | 0
回答済み
How to build a model using HDL coder library in simulink?
It is quite possible you have installed HDLCoder followed up Xilinx System Generator (XSG) in your machine and some how XSG inst...
How to build a model using HDL coder library in simulink?
It is quite possible you have installed HDLCoder followed up Xilinx System Generator (XSG) in your machine and some how XSG inst...
2ヶ月 前 | 0
回答済み
hdl coder work flow adviser block compability error
Running hdlsetup command on the model targeted for FPGA always helps in terms of data type selection. web(fullfile(docroot, 'h...
hdl coder work flow adviser block compability error
Running hdlsetup command on the model targeted for FPGA always helps in terms of data type selection. web(fullfile(docroot, 'h...
3ヶ月 前 | 2
回答済み
hardware implementation of NN code
Do you have access to these products? https://www.mathworks.com/products/gpu-coder.html GPU Coder™ generates optimized CUDA...
hardware implementation of NN code
Do you have access to these products? https://www.mathworks.com/products/gpu-coder.html GPU Coder™ generates optimized CUDA...
3ヶ月 前 | 0
| 採用済み
回答済み
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Please share sample MATLAB Code and Testbench and the error you are seeing. Thanks
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Please share sample MATLAB Code and Testbench and the error you are seeing. Thanks
3ヶ月 前 | 0
回答済み
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Can you share a sample code and testbench? See attached example on how to generate HDL from hdl.FFT function.
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Can you share a sample code and testbench? See attached example on how to generate HDL from hdl.FFT function.
3ヶ月 前 | 0
回答済み
can we generate HDL code for matrix multiplication ?
You can do this to open the models. The models do not use any new 20b features. https://www.mathworks.com/help//simulink/gui/si...
can we generate HDL code for matrix multiplication ?
You can do this to open the models. The models do not use any new 20b features. https://www.mathworks.com/help//simulink/gui/si...
3ヶ月 前 | 0
回答済み
can we generate HDL code for matrix multiplication ?
Attaching few flavors of matrix multiplication compatible with HDL Coder. matmul_external_memory_20b.slx matmul_mlfb_fixpt_...
can we generate HDL code for matrix multiplication ?
Attaching few flavors of matrix multiplication compatible with HDL Coder. matmul_external_memory_20b.slx matmul_mlfb_fixpt_...
3ヶ月 前 | 0
回答済み
How can I convert from decimal to binary for HDL Coder?
Attaching the model in the example for convenience.
How can I convert from decimal to binary for HDL Coder?
Attaching the model in the example for convenience.
3ヶ月 前 | 0
回答済み
Data type issue for LUT input
hdlcoderFocCurrentFixptHdl should generate HDL out of the box. >> makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control') ...
Data type issue for LUT input
hdlcoderFocCurrentFixptHdl should generate HDL out of the box. >> makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control') ...
4ヶ月 前 | 0
回答済み
hdlcoder std_logic_vector to stateflow type
Attached simple Stateflow chart will generate the code you are looking for.
hdlcoder std_logic_vector to stateflow type
Attached simple Stateflow chart will generate the code you are looking for.
4ヶ月 前 | 0
回答済み
can we generate HDL code for matrix multiplication ?
hi satish, can you share more details?are both A and B inputs to the DUT or only one of them, what are the types, are you lookin...
can we generate HDL code for matrix multiplication ?
hi satish, can you share more details?are both A and B inputs to the DUT or only one of them, what are the types, are you lookin...
4ヶ月 前 | 0
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .
Select web siteYou can also select a web site from the following list:
Americas
- América Latina (Español)
- Canada (English)
- United States (English)
Europe
- Belgium (English)
- Denmark (English)
- Deutschland (Deutsch)
- España (Español)
- Finland (English)
- France (Français)
- Ireland (English)
- Italia (Italiano)
- Luxembourg (English)
- Netherlands (English)
- Norway (English)
- Österreich (Deutsch)
- Portugal (English)
- Sweden (English)
- Switzerland
- United Kingdom (English)