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Kiran Kintali

Last seen: 4日 前 2011 以来アクティブ

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回答済み
up sample Simulink doesn't implement rate convertion on hdl coder
Please share your model. I do not see any such errors with a basic model with your sample settings.

4日 前 | 0

回答済み
Can HDL coder produce code for unit delay with initial condition input
This feature is not currently supported and is on the future HDL Coder roadmap. For the block 'model/DUTSubsystem/Delay' ...

4日 前 | 0

回答済み
PMSM is programed in FPGA using HDL coder.
In the motor control demo project the current control algorithm and speed control runs on FPGA and processor respectively and th...

11日 前 | 0

回答済み
PMSM is programed in FPGA using HDL coder.
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-pro...

16日 前 | 0

回答済み
Modeling S-R Flip flip for HDL code generation
Attached in an example model that works in 22a release.

22日 前 | 0

回答済み
The top design unit selected for HDL code generation may not be inside a triggered subsystem.
The DUT targeted for code generation can be a whole model with root ports, or a regular virtual or atomic subystem, model refere...

23日 前 | 0

回答済み
makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...

約1ヶ月 前 | 0

回答済み
What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...

約1ヶ月 前 | 0

回答済み
How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...

約1ヶ月 前 | 1

| 採用済み

回答済み
Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

約2ヶ月 前 | 0

回答済み
how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

約2ヶ月 前 | 0

回答済み
How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVER...

約2ヶ月 前 | 0

回答済み
Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

2ヶ月 前 | 1

回答済み
HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

3ヶ月 前 | 0

回答済み
Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

3ヶ月 前 | 0

回答済み
Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

3ヶ月 前 | 0

回答済み
Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

3ヶ月 前 | 0

回答済み
[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
How to use Matlab generated c code for vivado HLS ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
Compose High Level Synthesis (HLS) from Matlab code
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
How to use Matlab generated c code for High Level Synthesis ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 0

回答済み
Generate C code for HLS?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3ヶ月 前 | 1

回答済み
How to add a custom parameter in the generated module with HDL Coder,simulink?
How are generics supported in HDL Coder? https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supporte...

3ヶ月 前 | 0

| 採用済み

回答済み
HDL Code generation and deploy data onto the hardware board
For #1 Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ha...

3ヶ月 前 | 0

回答済み
HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...

4ヶ月 前 | 1

| 採用済み

回答済み
In HDL Simulink, How to convert from integer to boolean array.
https://www.mathworks.com/help/hdlcoder/ref/bitslice.html >> hdlcoder_int2bits_bits2int You can check this thread as well....

4ヶ月 前 | 0

回答済み
HDL supported block for integer to binary
can you try this example? >>hdlcoder_int2bits_bits2int

4ヶ月 前 | 0

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