Kiran Kintali

Last seen: 3日前 | 2011 年からアクティブ

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Programming Languages:
C++, MATLAB
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English, Hindi, Telugu
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Why do I receive a privimporthdl error when importing the operator.vhd example
VHDL Import is a new feature in R2024b release. https://www.mathworks.com/help/releases/R2024b/hdlcoder/release-notes.html?star...

6日前 | 0

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how to find abc_expected.dat file in MATLAB simulink model ?
HDL Coder generates RTL code (VHDL, Verilog, SystemVerilog) from the Design Under Test. It can also generate a RTL testbench f...

18日前 | 0

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Problem related to GUI deployment
In a fresh launch of MATLAB session repeat the above steps. When the error hits run the following command >> license inuse you...

23日前 | 0

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回答済み
struct memeber can not be Simulink.Parameter?
These pages contain good info on allowed ExportedGlobal usage in HDL Coder https://www.mathworks.com/help/hdlcoder/ug/generate-...

26日前 | 0

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generated rs code function result is not different with matlab simulink simulation
Are you using HDL Coder with this demo and not meeting timing? https://www.mathworks.com/help/wireless-hdl/ug/rsdecode.html op...

27日前 | 0

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How to properly use hdl.RAM for Matlab to VHDL conversion?
HDL Coder generated code should match the fixed point code. I see you are using coder.hdl.pipeline which are pipeline delays and...

約1ヶ月前 | 0

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HDL Coder; Matlab Function Blocks and Clocked Processes
For a subset of MATLAB with data flow semantics you may find MATLAB Function Block (Data Path Architecture) more suitable for ...

約2ヶ月前 | 0

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zcu102: split tasks between the 4 available CPUs
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-...

約2ヶ月前 | 0

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How to generate Generic VHDL from simulink for sysgen model?
HDL Coder by default generates generic RTL. The RTL is vendor independent but target optimized. The generated RTL can be taken t...

2ヶ月前 | 0

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Is there any method in simulink to Connect with Zynq ultrascale + MPSoC ZCU104 FPGA Board.
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html You c...

3ヶ月前 | 0

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Can we design a CNN Model in simulink
You may find these topics helpful Deep Learning in Simulink https://www.mathworks.com/help/deeplearning/deep-learning-with-s...

3ヶ月前 | 0

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how to use Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices in MATLAB ONLINE
Deep Learning HDL Toolbox and HDL Coder products are needed for exploring the FPGA/ASIC workflow. https://www.mathworks.com/p...

3ヶ月前 | 0

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HDL and NI FPGA code generation error.
You can generate HDL Code from the attached MATLAB function block performing RMS (root mean square) algorithm. % Generate HDL...

3ヶ月前 | 0

回答済み
How to generate simulink model from multiple verilog codes?
importhdl - Import Verilog code and generate Simulink model - MATLAB (mathworks.com) Please note HDL Coder only supports a subs...

3ヶ月前 | 0

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Rate Transition with a RAM Block
Can you please share your model? Thanks.

3ヶ月前 | 0

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issue with the IP
openExample('whdl/WHDLOFDMTransmitterExample') What kind of errors are you running into? Did you try R2024a or R2024b pre-rel...

3ヶ月前 | 0

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Documentation for HDL code generated
You can transfer model and code comments into the generated HDL code using HDL Coder. https://www.mathworks.com/help/hdlcoder/u...

3ヶ月前 | 0

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Call graph generation from VHDL code files.
https://www.mathworks.com/help/hdlcoder/hdl-import.html Does this help?

3ヶ月前 | 1

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Discrete integrator again fails to convert to Verilog due to delay balancing failure
>> hdlsaveparams('integrator/Integrator') fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hd...

3ヶ月前 | 2

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Discrete integrator again fails to convert to Verilog due to delay balancing failure
can you share the SignalBuilder.mat file?

3ヶ月前 | 1

回答済み
HDL Coder Generation Error
Can you please share your model or reach out to tech support? This is not expected behavior. What version of MATLAB are you usin...

3ヶ月前 | 0

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What to do after generating HDL code?
I am assuming you are using an evaluation FPGA board. Use traceability report to understand the elements of the generated code ...

3ヶ月前 | 1

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Why is the FPGA image for UHD different?
>> Does Mathworks allow the FPGA to be modified using the HDL Coder toolset? Yes, if you have an FPGA/SoC on the board you ca...

4ヶ月前 | 0

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how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
You may find these links helpful to reduce your area consumption on the hardware. https://www.mathworks.com/help/hdlcoder/ug/re...

4ヶ月前 | 1

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Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Simscape to HDL workflow if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit....

4ヶ月前 | 0

回答済み
fixing clock frequency and sample time of control system model using hdl coder
See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL C...

4ヶ月前 | 0

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errors with Simscape and SSC HDL Coder Workflow Advisor
It looks like this issue fixed in R2024a update4. https://www.mathworks.com/support/bugreports/3262131 Can you consider upgra...

4ヶ月前 | 0

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Does Simscape Specialized Power Systems blocks work with HDL Coder?
SPS blocks are not currently supported for HDL Code Generation. Please reach out to tech support and share your model of interes...

4ヶ月前 | 0

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errors with Simscape and SSC HDL Coder Workflow Advisor
Happy to diagnose this further. Would you be able share your model with us? Thanks.

4ヶ月前 | 0

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ive been trying to generate vhdl code using hdl code genrator on matlab 2020a but its showing error regarding the use of fi in my code , can someone fix it for me ? thankyou
Please review MATLAB design patterns here. https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-...

4ヶ月前 | 0

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