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Kiran Kintali

Last seen: 3日 前 |  2011 以来アクティブ

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回答済み
Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

11日 前 | 0

回答済み
how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

12日 前 | 0

回答済み
How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVER...

19日 前 | 0

回答済み
Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

約1ヶ月 前 | 1

回答済み
HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

約2ヶ月 前 | 0

回答済み
Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

約2ヶ月 前 | 0

回答済み
Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

約2ヶ月 前 | 0

回答済み
Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

2ヶ月 前 | 0

回答済み
[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
How to use Matlab generated c code for vivado HLS ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
Compose High Level Synthesis (HLS) from Matlab code
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
How to use Matlab generated c code for High Level Synthesis ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 0

回答済み
Generate C code for HLS?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

2ヶ月 前 | 1

回答済み
How to add a custom parameter in the generated module with HDL Coder,simulink?
How are generics supported in HDL Coder? https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supporte...

2ヶ月 前 | 0

| 採用済み

回答済み
HDL Code generation and deploy data onto the hardware board
For #1 Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ha...

2ヶ月 前 | 0

回答済み
HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...

3ヶ月 前 | 1

| 採用済み

回答済み
In HDL Simulink, How to convert from integer to boolean array.
https://www.mathworks.com/help/hdlcoder/ref/bitslice.html >> hdlcoder_int2bits_bits2int You can check this thread as well....

3ヶ月 前 | 0

回答済み
HDL supported block for integer to binary
can you try this example? >>hdlcoder_int2bits_bits2int

3ヶ月 前 | 0

回答済み
Update Diagram fails on "No Connect" Cosim block
Can you share a sample model with your usecase?

3ヶ月 前 | 0

回答済み
How to deploy matlab deep learning models to Texas Instruments?
DL code generated for library-free “none” target should be deployable on TI C2000. https://www.mathworks.com/videos/generate-...

3ヶ月 前 | 0

| 採用済み

回答済み
Vivado 2020.2 and HDL coder
HDL Coder generated VHDL/Verilog code is Vivado version independent and works with any version of the Xilinx software. For Viva...

3ヶ月 前 | 1

回答済み
Timing Constraint not met error for ZYNQ706
You can consider pipelining the design. See the timing related optimization section in HDL Coder https://www.mathworks.com/help/...

3ヶ月 前 | 0

回答済み
Numerator of FIR filter using "firpm" command is not working properly for ZYNQ 706
If your Simulink model has a testbench you can consider generating HDL code with the testbench and verify the generated code in ...

3ヶ月 前 | 0

回答済み
Colon operation in fixed-point
Support for colon exists with fixed-point types according to documentation. https://www.mathworks.com/help/fixedpoint/ref/colon....

3ヶ月 前 | 0

回答済み
how to fix inferring latch(es) for signal or variable holds its previous value in one or more paths through the process vhdl error
This could be a bug in code generation process. Can you reach out to https://www.mathworks.com/support.html?

3ヶ月 前 | 0

回答済み
Colon operation in fixed-point
MATLAB HDL Coder workflow does support colon operator during fixed-point conversion and code generation. Please share a sample d...

3ヶ月 前 | 0

回答済み
SIMPLE HDL code generation example
This example should help do basic LED blinking using a simple counter. Getting Started with Targeting Xilinx Zynq Platform ope...

3ヶ月 前 | 0

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