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Deep Learning HDL Toolbox + Quartus Pro 23.3
Please check the HDL Coder supported version of Intel Quartus with R2024a and R2024b releases. https://www.mathworks.com/help/r...
Deep Learning HDL Toolbox + Quartus Pro 23.3
Please check the HDL Coder supported version of Intel Quartus with R2024a and R2024b releases. https://www.mathworks.com/help/r...
4日 前 | 0
回答済み
how to download the third party support package file "xilinx linux binaries"
What version of MATLAB are you using? Please do not hesitate to reach out to tech support.
how to download the third party support package file "xilinx linux binaries"
What version of MATLAB are you using? Please do not hesitate to reach out to tech support.
7日 前 | 0
回答済み
Seeking Guidance on Auto-Generating Verilog Code for ASIC Simulation with HDL Coder and Deep Learning HDL Toolbox
Classify ECG Signals Using DAG Network Deployed to FPGA This example shows how to classify human electrocardiogram (ECG) signal...
Seeking Guidance on Auto-Generating Verilog Code for ASIC Simulation with HDL Coder and Deep Learning HDL Toolbox
Classify ECG Signals Using DAG Network Deployed to FPGA This example shows how to classify human electrocardiogram (ECG) signal...
21日 前 | 0
回答済み
Characterisation error in HDL code generation?
This is an unexpected error. What version of MATLAB are you using? Can you share the model? Do not hesitate to reach out to te...
Characterisation error in HDL code generation?
This is an unexpected error. What version of MATLAB are you using? Can you share the model? Do not hesitate to reach out to te...
28日 前 | 0
回答済み
Why do I receive a privimporthdl error when importing the operator.vhd example
VHDL Import is a new feature in R2024b release. https://www.mathworks.com/help/releases/R2024b/hdlcoder/release-notes.html?star...
Why do I receive a privimporthdl error when importing the operator.vhd example
VHDL Import is a new feature in R2024b release. https://www.mathworks.com/help/releases/R2024b/hdlcoder/release-notes.html?star...
約1ヶ月 前 | 0
回答済み
how to find abc_expected.dat file in MATLAB simulink model ?
HDL Coder generates RTL code (VHDL, Verilog, SystemVerilog) from the Design Under Test. It can also generate a RTL testbench f...
how to find abc_expected.dat file in MATLAB simulink model ?
HDL Coder generates RTL code (VHDL, Verilog, SystemVerilog) from the Design Under Test. It can also generate a RTL testbench f...
約2ヶ月 前 | 0
| 採用済み
回答済み
Problem related to GUI deployment
In a fresh launch of MATLAB session repeat the above steps. When the error hits run the following command >> license inuse you...
Problem related to GUI deployment
In a fresh launch of MATLAB session repeat the above steps. When the error hits run the following command >> license inuse you...
約2ヶ月 前 | 0
| 採用済み
回答済み
struct memeber can not be Simulink.Parameter?
These pages contain good info on allowed ExportedGlobal usage in HDL Coder https://www.mathworks.com/help/hdlcoder/ug/generate-...
struct memeber can not be Simulink.Parameter?
These pages contain good info on allowed ExportedGlobal usage in HDL Coder https://www.mathworks.com/help/hdlcoder/ug/generate-...
約2ヶ月 前 | 0
回答済み
generated rs code function result is not different with matlab simulink simulation
Are you using HDL Coder with this demo and not meeting timing? https://www.mathworks.com/help/wireless-hdl/ug/rsdecode.html op...
generated rs code function result is not different with matlab simulink simulation
Are you using HDL Coder with this demo and not meeting timing? https://www.mathworks.com/help/wireless-hdl/ug/rsdecode.html op...
約2ヶ月 前 | 0
回答済み
How to properly use hdl.RAM for Matlab to VHDL conversion?
HDL Coder generated code should match the fixed point code. I see you are using coder.hdl.pipeline which are pipeline delays and...
How to properly use hdl.RAM for Matlab to VHDL conversion?
HDL Coder generated code should match the fixed point code. I see you are using coder.hdl.pipeline which are pipeline delays and...
約2ヶ月 前 | 0
回答済み
HDL Coder; Matlab Function Blocks and Clocked Processes
For a subset of MATLAB with data flow semantics you may find MATLAB Function Block (Data Path Architecture) more suitable for ...
HDL Coder; Matlab Function Blocks and Clocked Processes
For a subset of MATLAB with data flow semantics you may find MATLAB Function Block (Data Path Architecture) more suitable for ...
3ヶ月 前 | 0
回答済み
zcu102: split tasks between the 4 available CPUs
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-...
zcu102: split tasks between the 4 available CPUs
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-...
3ヶ月 前 | 0
回答済み
How to generate Generic VHDL from simulink for sysgen model?
HDL Coder by default generates generic RTL. The RTL is vendor independent but target optimized. The generated RTL can be taken t...
How to generate Generic VHDL from simulink for sysgen model?
HDL Coder by default generates generic RTL. The RTL is vendor independent but target optimized. The generated RTL can be taken t...
3ヶ月 前 | 0
回答済み
Is there any method in simulink to Connect with Zynq ultrascale + MPSoC ZCU104 FPGA Board.
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html You c...
Is there any method in simulink to Connect with Zynq ultrascale + MPSoC ZCU104 FPGA Board.
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html You c...
4ヶ月 前 | 0
回答済み
Can we design a CNN Model in simulink
You may find these topics helpful Deep Learning in Simulink https://www.mathworks.com/help/deeplearning/deep-learning-with-s...
Can we design a CNN Model in simulink
You may find these topics helpful Deep Learning in Simulink https://www.mathworks.com/help/deeplearning/deep-learning-with-s...
4ヶ月 前 | 0
| 採用済み
回答済み
how to use Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices in MATLAB ONLINE
Deep Learning HDL Toolbox and HDL Coder products are needed for exploring the FPGA/ASIC workflow. https://www.mathworks.com/p...
how to use Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices in MATLAB ONLINE
Deep Learning HDL Toolbox and HDL Coder products are needed for exploring the FPGA/ASIC workflow. https://www.mathworks.com/p...
4ヶ月 前 | 0
回答済み
HDL and NI FPGA code generation error.
You can generate HDL Code from the attached MATLAB function block performing RMS (root mean square) algorithm. % Generate HDL...
HDL and NI FPGA code generation error.
You can generate HDL Code from the attached MATLAB function block performing RMS (root mean square) algorithm. % Generate HDL...
4ヶ月 前 | 0
回答済み
How to generate simulink model from multiple verilog codes?
importhdl - Import Verilog code and generate Simulink model - MATLAB (mathworks.com) Please note HDL Coder only supports a subs...
How to generate simulink model from multiple verilog codes?
importhdl - Import Verilog code and generate Simulink model - MATLAB (mathworks.com) Please note HDL Coder only supports a subs...
4ヶ月 前 | 0
回答済み
issue with the IP
openExample('whdl/WHDLOFDMTransmitterExample') What kind of errors are you running into? Did you try R2024a or R2024b pre-rel...
issue with the IP
openExample('whdl/WHDLOFDMTransmitterExample') What kind of errors are you running into? Did you try R2024a or R2024b pre-rel...
4ヶ月 前 | 0
回答済み
Documentation for HDL code generated
You can transfer model and code comments into the generated HDL code using HDL Coder. https://www.mathworks.com/help/hdlcoder/u...
Documentation for HDL code generated
You can transfer model and code comments into the generated HDL code using HDL Coder. https://www.mathworks.com/help/hdlcoder/u...
4ヶ月 前 | 0
回答済み
Call graph generation from VHDL code files.
https://www.mathworks.com/help/hdlcoder/hdl-import.html Does this help?
Call graph generation from VHDL code files.
https://www.mathworks.com/help/hdlcoder/hdl-import.html Does this help?
4ヶ月 前 | 1
| 採用済み
回答済み
Discrete integrator again fails to convert to Verilog due to delay balancing failure
>> hdlsaveparams('integrator/Integrator') fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hd...
Discrete integrator again fails to convert to Verilog due to delay balancing failure
>> hdlsaveparams('integrator/Integrator') fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hd...
4ヶ月 前 | 2
| 採用済み
回答済み
Discrete integrator again fails to convert to Verilog due to delay balancing failure
can you share the SignalBuilder.mat file?
Discrete integrator again fails to convert to Verilog due to delay balancing failure
can you share the SignalBuilder.mat file?
4ヶ月 前 | 1
回答済み
HDL Coder Generation Error
Can you please share your model or reach out to tech support? This is not expected behavior. What version of MATLAB are you usin...
HDL Coder Generation Error
Can you please share your model or reach out to tech support? This is not expected behavior. What version of MATLAB are you usin...
4ヶ月 前 | 0
回答済み
What to do after generating HDL code?
I am assuming you are using an evaluation FPGA board. Use traceability report to understand the elements of the generated code ...
What to do after generating HDL code?
I am assuming you are using an evaluation FPGA board. Use traceability report to understand the elements of the generated code ...
4ヶ月 前 | 1
| 採用済み
回答済み
Why is the FPGA image for UHD different?
>> Does Mathworks allow the FPGA to be modified using the HDL Coder toolset? Yes, if you have an FPGA/SoC on the board you ca...
Why is the FPGA image for UHD different?
>> Does Mathworks allow the FPGA to be modified using the HDL Coder toolset? Yes, if you have an FPGA/SoC on the board you ca...
5ヶ月 前 | 0
回答済み
how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
You may find these links helpful to reduce your area consumption on the hardware. https://www.mathworks.com/help/hdlcoder/ug/re...
how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
You may find these links helpful to reduce your area consumption on the hardware. https://www.mathworks.com/help/hdlcoder/ug/re...
5ヶ月 前 | 1
| 採用済み
回答済み
Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Simscape to HDL workflow if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit....
Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Simscape to HDL workflow if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit....
5ヶ月 前 | 0
回答済み
fixing clock frequency and sample time of control system model using hdl coder
See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL C...
fixing clock frequency and sample time of control system model using hdl coder
See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL C...
5ヶ月 前 | 0