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issue with the IP
openExample('whdl/WHDLOFDMTransmitterExample') What kind of errors are you running into? Did you try R2024a or R2024b pre-rel...

8ヶ月前 | 0

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Documentation for HDL code generated
You can transfer model and code comments into the generated HDL code using HDL Coder. https://www.mathworks.com/help/hdlcoder/u...

8ヶ月前 | 0

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Call graph generation from VHDL code files.
https://www.mathworks.com/help/hdlcoder/hdl-import.html Does this help?

8ヶ月前 | 1

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Discrete integrator again fails to convert to Verilog due to delay balancing failure
>> hdlsaveparams('integrator/Integrator') fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hd...

8ヶ月前 | 2

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Discrete integrator again fails to convert to Verilog due to delay balancing failure
can you share the SignalBuilder.mat file?

8ヶ月前 | 1

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HDL Coder Generation Error
Can you please share your model or reach out to tech support? This is not expected behavior. What version of MATLAB are you usin...

8ヶ月前 | 0

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What to do after generating HDL code?
I am assuming you are using an evaluation FPGA board. Use traceability report to understand the elements of the generated code ...

8ヶ月前 | 1

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Why is the FPGA image for UHD different?
>> Does Mathworks allow the FPGA to be modified using the HDL Coder toolset? Yes, if you have an FPGA/SoC on the board you ca...

8ヶ月前 | 0

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how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
You may find these links helpful to reduce your area consumption on the hardware. https://www.mathworks.com/help/hdlcoder/ug/re...

8ヶ月前 | 1

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Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Simscape to HDL workflow if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit....

8ヶ月前 | 0

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fixing clock frequency and sample time of control system model using hdl coder
See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL C...

8ヶ月前 | 0

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errors with Simscape and SSC HDL Coder Workflow Advisor
It looks like this issue fixed in R2024a update4. https://www.mathworks.com/support/bugreports/3262131 Can you consider upgra...

8ヶ月前 | 0

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Does Simscape Specialized Power Systems blocks work with HDL Coder?
SPS blocks are not currently supported for HDL Code Generation. Please reach out to tech support and share your model of interes...

8ヶ月前 | 0

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errors with Simscape and SSC HDL Coder Workflow Advisor
Happy to diagnose this further. Would you be able share your model with us? Thanks.

8ヶ月前 | 0

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ive been trying to generate vhdl code using hdl code genrator on matlab 2020a but its showing error regarding the use of fi in my code , can someone fix it for me ? thankyou
Please review MATLAB design patterns here. https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-...

8ヶ月前 | 0

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What is the reason for error in HDL Coder and Cadence Stratus HLS tutorial?
openExample('hdlcoder/GetStartedWithMATLABToSystemCWorkflowUsingHDLCoderAppExample') https://www.mathworks.com/help/hdlcoder/gs...

8ヶ月前 | 0

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HDL Tool setup issue
Step1: First check if Vivado is on your system path in your command window. Find out the location of the vivado from within MA...

8ヶ月前 | 0

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how can I covert my customize MATLAB to HDl code
This page provides some examples and workflows for HDL code generation from MATLAB and Simulink. https://www.mathworks.com/ma...

8ヶ月前 | 0

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OFDM implementation over rayleigh channel with doppler , matlab(simulink) to hdl
These two examples might be helpful. https://www.mathworks.com/help/wireless-hdl/ug/hdlofdmtransmitter.html https://www.mathwo...

8ヶ月前 | 0

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What is the reason for error in HDL Coder and Cadence Stratus HLS tutorial?
We are not aware of such issues with Stratus integration. The error seems to happen post MATLAB to SystemC translation during St...

8ヶ月前 | 0

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Atan2 block native floating point single HDL generation needs more pipelining
Improved performance for Atan2 block in the R2024a release. HDL Coder has enhanced the design implementation of the Atan2 block...

9ヶ月前 | 0

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How to get Simulink HDL Coder RAM with non power of 2 depth.
Does this solve your usecase? function y = ramBanksScalarInput(u, addr) % addr --> 12bits % u --> uint8 persistent ram...

9ヶ月前 | 0

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How to get Simulink HDL Coder RAM with non power of 2 depth.
I wonder if you can use the RAM banks feature in HDL Coder. https://www.mathworks.com/help/hdlcoder/ref/hdl.ram-system-object...

9ヶ月前 | 0

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Assertion failed error while convereting simulink model to HDL code
Can you please share your model? This error message is not expected. Thanks.

9ヶ月前 | 0

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Adaptive pipelining design cannot insert the required number of registers in a feedback loop with integral modules
What version of MATLAB are you using? Can you please share your model? Have you tried using Oversampling factor (>1) to allocat...

9ヶ月前 | 0

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Failed Generated HDL code, testbench.
The model on the left has root ports; no stimulus/source blocks in the Simulink. The model on the right has valid sources/...

10ヶ月前 | 0

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Examples of Simulink models of spacecraft subsystems controlled by FPGA algorithms
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-referenc...

10ヶ月前 | 1

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Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
Can you reach out to tech support? I am not sure if this could be Vivado version related issue.

10ヶ月前 | 0

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Delay balancing error while using HDL coder
Hi Sanil, would you be able to share your model? Do not hesitate to reach to technical support and we can help further assist y...

10ヶ月前 | 0

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Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
https://www.mathworks.com/help/hdlcoder/ug/simscape-hil-speedgoat-fpga-io-modules.html What version of synthesis tools AMD/Xi...

10ヶ月前 | 0