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HDLCoder The Block/HDLImplementation pair: ('modelsimlib/HDL Cosimulation', 'hdldefaults.ModelSimHDLInstantiation') is not registered in the implementation database.
should be the same underlying install issue you are facing here. https://www.mathworks.com/matlabcentral/answers/889352-unrecog...

3ヶ月 前 | 0

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How to store the output of a repeating function (Matlab Function Block Simulink) ?
% Hardware friendly implementation of peak finder % % Function inputs: % * WindowLen - non-tunable parameter defined un...

3ヶ月 前 | 0

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struct memeber can not be Simulink.Parameter?
Can you share a sample model?

3ヶ月 前 | 0

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Unrecognized function or variable 'vsim'.
https://www.mathworks.com/support/contact_us.html please reach out to support for this install question.

3ヶ月 前 | 0

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Unrecognized function or variable 'vsim'.
Possibly install issue. Do you have this file on your path? >> help vsim vsim Launch ModelSim for use with MATLAB and Simul...

3ヶ月 前 | 1

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Convert MATLAB ANN Model to HDL using HDL Coder
Can you share reproduction steps? Thanks

3ヶ月 前 | 0

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Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices
Please follow guidance from this thread. https://www.mathworks.com/matlabcentral/answers/882868-deep-learning-hdl-toolbox-suppo...

3ヶ月 前 | 0

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Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices
We understand you running into the issue during the hardware support package setup, while downloading the Linux image. Can you c...

3ヶ月 前 | 0

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start hdl coder from simulink model
We have seen this error when the DUT specification has a newline character. Launching HDL Coder app button in toolstrip has this...

3ヶ月 前 | 0

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HDLCoder timing closure errors on hps2fpga brigde when scaling up a model.
You can reach out to support@mathworks.com to get additional help on the topic.

3ヶ月 前 | 0

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HDLCoder timing closure errors on hps2fpga brigde when scaling up a model.
>> Im trying to scale up a motor control algorithm from 1 controller to 4 instances on HDLCoder This should be possible. Can yo...

3ヶ月 前 | 0

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how to generate sine wave for fpga?
Attached model generates HDL Code using HDL Coder. >> makehdl(gcb) ### Generating HDL for 'sine_cust_hdl/WaveGen HDL'....

3ヶ月 前 | 0

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How do I convert between enumeration and integer types for use with HDL Coder?
Updated Answer (R2021a) HDL Code Generation for Data Type Conversion block supports enumerated data types in R2021a release. ...

3ヶ月 前 | 1

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Making Simulink HDL Coder with Dynamic Input.
What version of MATLAB are you using? I am able to generate code for the 'masters_v5/DUT/HDL DUT' subsystem >> makehdl(gc...

3ヶ月 前 | 0

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simulink _hdl coder
>> Error: Evaluation of emission function on class hdldefaults.Subsystem failed with the error message: >> MATLAB:UndefinedFunc...

3ヶ月 前 | 0

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Simulink to HDL
>> Error: Evaluation of emission function on class hdldefaults.Subsystem failed with the error message: >> MATLAB:UndefinedFunc...

3ヶ月 前 | 0

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How do I convert a fixed point or integer word to array of bits and vice versa?
Attached model in this repository shows how to do this using MATLAB Function Blocks. https://github.com/mw-kirank/HDL-Bit-Opera...

4ヶ月 前 | 0

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質問


How do I convert a fixed point or integer word to array of bits and vice versa?
How do I build a model to convert word to bits and bits to word and generate HDL using HDL Coder?

4ヶ月 前 | 1 件の回答 | 0

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Serial communication through Matlab
This page can be helpful for this topic. https://www.mathworks.com/help/supportpkg/xilinxfpgaturnkeyboards/index.html

4ヶ月 前 | 0

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Merging separate vivado project into RF SOM reference design and using external target interface
If this question is about merging multiple IP blocks built under different projects into a single bitstream, please contact supp...

4ヶ月 前 | 0

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please help me to fix this error " HDL code generation for fixed point division is only supported when 'RoundMode' is 'Fix' or 'Nearest' "
If this is staill an issue please share dut.m (design) and testbench.m (testbench calling the design) and a project file that is...

4ヶ月 前 | 0

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simulink model to hdl code
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide please refer to getting start...

4ヶ月 前 | 0

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How can I control the HDL FIFO in simulink to send data to the I/O of the De1soc for a given frequency?
Define Custom Board and Reference Design for Intel SoC Workflow https://ww2.mathworks.cn/help/hdlcoder/ug/define-and-register-c...

4ヶ月 前 | 0

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Data Loos in a multi rate system in HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/authoring-a-reference-design-for-audio-system-on-a-zynq-board.html Authoring a Ref...

4ヶ月 前 | 0

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Error using exampleUtils.componentExamplesDir
This seems to be an installation issue. Can you try reinstall and if that doesn't work, can you contact support@mathworks.com?...

4ヶ月 前 | 0

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Zedboard Sine wave implementation problem
Attached is a simple sine wave generation example suitable for HDL code generation.

4ヶ月 前 | 0

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Getting multiple outputs on a single variable in MATLAB function block inside simulink.
Use this example to see how to extract a port of the image to stream into DUT suitable for HDL Code Generation.

4ヶ月 前 | 0

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Problems encountered when converting simulink model, including From File block, to hdl code.
FromFileBlock can be used only as a source in the test bench outside the design under test (DUT). The source block is not suppor...

4ヶ月 前 | 0

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HDL Coder output port type needs to be std_logic_vector (8 downto 0)
Consider using hdlsetup command, it puts the model in ASIC/FPGA mode which generates full-precision arithmetic suitable for AS...

4ヶ月 前 | 0

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