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how to fix inferring latch(es) for signal or variable holds its previous value in one or more paths through the process vhdl error
This could be a bug in code generation process. Can you reach out to https://www.mathworks.com/support.html?

3ヶ月 前 | 0

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Colon operation in fixed-point
MATLAB HDL Coder workflow does support colon operator during fixed-point conversion and code generation. Please share a sample d...

3ヶ月 前 | 0

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SIMPLE HDL code generation example
This example should help do basic LED blinking using a simple counter. Getting Started with Targeting Xilinx Zynq Platform ope...

4ヶ月 前 | 0

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Error while generating HDL code from Matlab: Invalid data type. H must be double.
Can you share your design.m, testbench.m files and the project file with necessary settings? Thanks

4ヶ月 前 | 0

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Connection Failed in hardware setup
https://www.mathworks.com/support.html Please reach out to support team on this topic.

4ヶ月 前 | 0

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i m trying using converting signal processing block into hdl code , but some of the blocks are not compatible into hdl conversion .does anyone knows how to do it
https://www.mathworks.com/help/radar/ug/automotive-adaptive-cruise-control-using-fmcw-and-mfsk-technology.html This example is ...

4ヶ月 前 | 0

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error after targheting xilinx Virtex UltraScale+ VCU118.
Possible pilot error in setting up the custom reference design or board support package. Please contact https://www.mathworks.c...

4ヶ月 前 | 0

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Why do I receive error Output argument "file_name" (and maybe others) not assigned during call to "mdlAdv_Scripts_Run.get_config_file"
I couldn't find the class/structure mdlAdv_Scripts_Run and method/member get_config_file in HDL Workflow Advisor. Guessing poss...

4ヶ月 前 | 0

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HDL IP Core generation for Xilinx Vivado fails since the year turned from 2021 to 2022
HDL IP core generation using Xilinx Vivado fails as of January 1, 2022 (2656440) https://www.mathworks.com/support/bugreports/2...

4ヶ月 前 | 0

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Error " Dot indexing is not supported for variable of this type" comes when tried to configure HDL Coder support package for Xilinx Zynq Platform.
MathWorks team is investigating the issue and will provide an update shortly. Any additional reproduction steps are helpful (mac...

4ヶ月 前 | 0

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Assertion failed: B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
Here is an example of HDL Coder friendly current control algorithm for your reference. Field-Oriented Control of a Permanent Ma...

5ヶ月 前 | 0

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Assertion failed: B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
This example is not compatible with HDL Code Generation. Reaching to the development team for suggestions on HDL Coder compatibl...

5ヶ月 前 | 1

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matlab hdl coder error
See detailed examples of how to perform HDL Code Generation from MATLAB — Examples

5ヶ月 前 | 0

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How to build a model that is efficient for HDL conversion?
DVB-S2 HDL PL Header Recovery This example shows how to implement DVB-S2 time, frequency, and phase synchronization and PL head...

5ヶ月 前 | 1

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Simulink model not editable
This example shows how to implement a QPSK transmitter and receiver in Simulink® that is optimized for HDL code generation and h...

5ヶ月 前 | 0

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HDL Coversion of Simulink code
HDL QPSK Transmitter and Receiver This example shows how to implement a QPSK transmitter and receiver in Simulink® that is opti...

5ヶ月 前 | 0

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how to convert matlab code in VHDL ? which tool boxes to download?
You need to partition the MATLAB code into design and testbench files and create a HDL Coder project. Try a sample MATLAB to HD...

6ヶ月 前 | 0

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How i can import an existing IP Core in Vivado in Simulink as block?
These links show how to integrate custom RTL code into a model targeted for HDL code generation using HDL Coder https://www.mat...

6ヶ月 前 | 0

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HDL coder fails generating wavelet denoise function
Support for C/C++ code generation exists for wdenoise. I have reported the HDL Code Generation request for this function to dev...

6ヶ月 前 | 0

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Using std_logic_vector(0 downto 0) in HDL Coder
Unfortunately this coding style switch is not currently available. I have communicated this request with the development team. ...

6ヶ月 前 | 0

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error in dlhdl.buildProcessor(hPCNew) step
Can you share the version of MATLAB you are using?

6ヶ月 前 | 0

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Explanation of "Assertion failed port already connected to signal error" when generating using HDL Coder?
We are unable to reproduce the issue on our end with the attached models. Please reach out to support for additional help on thi...

6ヶ月 前 | 0

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how to create bit from image to feed as input to xilinx multiplier block in system generator
Check this example on how to convert a frame to a sample and feed the sample into FPGA >> mlhdlc_demo_setup('heq')

6ヶ月 前 | 0

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Unable to create project in xilinx vivado 2015.2 from simulink using hdl workflow adviser,Getting error [12-172],how can get pass this?
https://www.mathworks.com/help/hdlcoder/ug/using-ip-core-generation-from-matlab.html Generate Custom HDL IP Core for Blinking L...

6ヶ月 前 | 0

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hdl coder IO buffer error
Answering the question without access to the model or the full context here. You could consider enabling the resource utiliza...

6ヶ月 前 | 1

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HDL Coder removes I/Os of a model reference when they are terminated inside the model reference
Remove Redundant Logic and Unused Blocks in Generated HDL Code https://www.mathworks.com/help/hdlcoder/ug/remove-redundant-lo...

6ヶ月 前 | 0

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Generate HDL Code for Simscape Models
The model does not show failures in HDL Coder R2020a and R2020b releases. Can you please sure additional information or reach o...

6ヶ月 前 | 0

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Inferring RAM zero index issue
Can you MATLAB code (dut.m) and a Testbench (dut_tb.m) and the project file with MATLAB to HDL codegen settings? This example...

6ヶ月 前 | 0

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Explanation of "Assertion failed port already connected to signal error" when generating using HDL Coder?
This is an unexpected internal error. Reported to the development team. Can you let us know what version of MATLAB / HDL Coder...

6ヶ月 前 | 0

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Generate HDL Code for Simscape Models
Can you share your Simscape model?

7ヶ月 前 | 0

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