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HDLCoder timing closure errors on hps2fpga brigde when scaling up a model.
You can reach out to support@mathworks.com to get additional help on the topic.

5ヶ月 前 | 0

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HDLCoder timing closure errors on hps2fpga brigde when scaling up a model.
>> Im trying to scale up a motor control algorithm from 1 controller to 4 instances on HDLCoder This should be possible. Can yo...

5ヶ月 前 | 0

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how to generate sine wave for fpga?
Attached model generates HDL Code using HDL Coder. >> makehdl(gcb) ### Generating HDL for 'sine_cust_hdl/WaveGen HDL'....

5ヶ月 前 | 0

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How do I convert between enumeration and integer types for use with HDL Coder?
Updated Answer (R2021a) HDL Code Generation for Data Type Conversion block supports enumerated data types in R2021a release. ...

5ヶ月 前 | 1

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Making Simulink HDL Coder with Dynamic Input.
What version of MATLAB are you using? I am able to generate code for the 'masters_v5/DUT/HDL DUT' subsystem >> makehdl(gc...

5ヶ月 前 | 0

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simulink _hdl coder
>> Error: Evaluation of emission function on class hdldefaults.Subsystem failed with the error message: >> MATLAB:UndefinedFunc...

5ヶ月 前 | 0

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Simulink to HDL
>> Error: Evaluation of emission function on class hdldefaults.Subsystem failed with the error message: >> MATLAB:UndefinedFunc...

5ヶ月 前 | 0

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How do I convert a fixed point or integer word to array of bits and vice versa?
Attached model in this repository shows how to do this using MATLAB Function Blocks. https://github.com/mw-kirank/HDL-Bit-Opera...

5ヶ月 前 | 0

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質問


How do I convert a fixed point or integer word to array of bits and vice versa?
How do I build a model to convert word to bits and bits to word and generate HDL using HDL Coder?

5ヶ月 前 | 1 件の回答 | 0

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Serial communication through Matlab
This page can be helpful for this topic. https://www.mathworks.com/help/supportpkg/xilinxfpgaturnkeyboards/index.html

5ヶ月 前 | 0

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Merging separate vivado project into RF SOM reference design and using external target interface
If this question is about merging multiple IP blocks built under different projects into a single bitstream, please contact supp...

5ヶ月 前 | 0

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please help me to fix this error " HDL code generation for fixed point division is only supported when 'RoundMode' is 'Fix' or 'Nearest' "
If this is staill an issue please share dut.m (design) and testbench.m (testbench calling the design) and a project file that is...

5ヶ月 前 | 0

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simulink model to hdl code
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide please refer to getting start...

5ヶ月 前 | 0

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How can I control the HDL FIFO in simulink to send data to the I/O of the De1soc for a given frequency?
Define Custom Board and Reference Design for Intel SoC Workflow https://ww2.mathworks.cn/help/hdlcoder/ug/define-and-register-c...

5ヶ月 前 | 0

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Data Loos in a multi rate system in HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/authoring-a-reference-design-for-audio-system-on-a-zynq-board.html Authoring a Ref...

5ヶ月 前 | 0

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Error using exampleUtils.componentExamplesDir
This seems to be an installation issue. Can you try reinstall and if that doesn't work, can you contact support@mathworks.com?...

5ヶ月 前 | 0

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Zedboard Sine wave implementation problem
Attached is a simple sine wave generation example suitable for HDL code generation.

5ヶ月 前 | 0

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Getting multiple outputs on a single variable in MATLAB function block inside simulink.
Use this example to see how to extract a port of the image to stream into DUT suitable for HDL Code Generation.

5ヶ月 前 | 0

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Problems encountered when converting simulink model, including From File block, to hdl code.
FromFileBlock can be used only as a source in the test bench outside the design under test (DUT). The source block is not suppor...

5ヶ月 前 | 0

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HDL Coder output port type needs to be std_logic_vector (8 downto 0)
Consider using hdlsetup command, it puts the model in ASIC/FPGA mode which generates full-precision arithmetic suitable for AS...

5ヶ月 前 | 0

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hdl code generation from simulink model
All input ports are connected to DUT shold be connected with valid sample times. Run "hdlsetup" command and make sure all sampl...

6ヶ月 前 | 0

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Error " Dot indexing is not supported for variable of this type" comes when tried to configure HDL Coder support package for Xilinx Zynq Platform.
This is not expected behavior. Can you share the issue and model/version details to support@mathworks.com?

6ヶ月 前 | 1

回答済み
MATLAB 2018a HDL-coder : Failed Program target FPGA device.
(per Kiyoko notes) There are some old ISE reference designs shipped in Zynq Hardware Support Package. These cause confusion. H...

6ヶ月 前 | 0

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HDL Coder giving Conformance error due to fi division
Without dut.m and testbench.m files and a MATLAB HDL Coder project it woudl be difficult to do further analysis. running the ...

6ヶ月 前 | 0

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Blackbox Interface : Task "Build FPGA Bitstream" unsuccessful
Do one of the two things below before running synthesis. If you use blackbox interface you need to provide the necessary HDL ar...

6ヶ月 前 | 0

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HDL Coder: Matlab stops working at code generation when generating high-level timing critical path report (Matlab 2015b)
You can check if this issue is already resolved. https://www.mathworks.com/support/bugreports/?&product[]=HD Reproduction step...

6ヶ月 前 | 0

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Code generation option in HDL coder for high clock frequency
Use critical path estimation feature to estimate the critical path in your model. This workflow in HDL Coder does not involve sy...

6ヶ月 前 | 0

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No system or file called 'axiinterfacelib' found
If the Embedded Coder Hardware Support package for Zynq is not installed, HDL Workflow Advisor is throwing the following unhelpf...

6ヶ月 前 | 1

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How can I call filter coefficients in bit reversed order for HDL FFT?
This question can best addressed by Vivado System Generator support team at https://www.xilinx.com

6ヶ月 前 | 0

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How to generate Verilog code from Deep Learning Network in MATLAB?
Deep Learning Processor Customization and IP Generation Configure, build, and generate custom bitstreams and processor IP cores...

6ヶ月 前 | 0

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