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HDL Coder output port type needs to be std_logic_vector (8 downto 0)
Consider using hdlsetup command, it puts the model in ASIC/FPGA mode which generates full-precision arithmetic suitable for AS...

7ヶ月 前 | 0

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hdl code generation from simulink model
All input ports are connected to DUT shold be connected with valid sample times. Run "hdlsetup" command and make sure all sampl...

7ヶ月 前 | 0

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Error " Dot indexing is not supported for variable of this type" comes when tried to configure HDL Coder support package for Xilinx Zynq Platform.
This is not expected behavior. Can you share the issue and model/version details to support@mathworks.com?

7ヶ月 前 | 1

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MATLAB 2018a HDL-coder : Failed Program target FPGA device.
(per Kiyoko notes) There are some old ISE reference designs shipped in Zynq Hardware Support Package. These cause confusion. H...

7ヶ月 前 | 0

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HDL Coder giving Conformance error due to fi division
Without dut.m and testbench.m files and a MATLAB HDL Coder project it woudl be difficult to do further analysis. running the ...

7ヶ月 前 | 0

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Blackbox Interface : Task "Build FPGA Bitstream" unsuccessful
Do one of the two things below before running synthesis. If you use blackbox interface you need to provide the necessary HDL ar...

7ヶ月 前 | 0

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HDL Coder: Matlab stops working at code generation when generating high-level timing critical path report (Matlab 2015b)
You can check if this issue is already resolved. https://www.mathworks.com/support/bugreports/?&product[]=HD Reproduction step...

7ヶ月 前 | 0

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Code generation option in HDL coder for high clock frequency
Use critical path estimation feature to estimate the critical path in your model. This workflow in HDL Coder does not involve sy...

7ヶ月 前 | 0

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No system or file called 'axiinterfacelib' found
If the Embedded Coder Hardware Support package for Zynq is not installed, HDL Workflow Advisor is throwing the following unhelpf...

7ヶ月 前 | 1

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How can I call filter coefficients in bit reversed order for HDL FFT?
This question can best addressed by Vivado System Generator support team at https://www.xilinx.com

7ヶ月 前 | 0

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How to generate Verilog code from Deep Learning Network in MATLAB?
Deep Learning Processor Customization and IP Generation Configure, build, and generate custom bitstreams and processor IP cores...

7ヶ月 前 | 0

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HDL synthesis doen't end?
It is possible you have very high resource usage or timing issue with your generated code. You should consider using high leve...

8ヶ月 前 | 0

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How can I force HDL Coder to use DSP48 slices?
if you are looking to automate DSP usage improvements you can consider using Adaptive pipelining optimization in HDL Coder. Ada...

8ヶ月 前 | 0

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How to update template on multiple Simulink models (programmatically)?
https://www.mathworks.com/help/hdlcoder/ug/hdl-coder-simulink-templates.html Use Simulink Templates for HDL Code Generation HD...

8ヶ月 前 | 0

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IP core generation zedboard FMCOMMS2 gives 2 critical warning in Vivado
web(fullfile(docroot, 'hdlcoder/ug/hdlqpsktransmitterandreceiver.html?s_tid=doc_srchtitle'))

8ヶ月 前 | 0

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Can I use a IFFT HDL Optimized block with an input length greater than 2^16?
https://www.mathworks.com/help/dsp/ref/dsp.hdlfft-system-object.html FFT length — Number of data points used for one FFT calcul...

8ヶ月 前 | 0

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Issues: FIR filter by HDL Coder on Redpitaya platform
>> mlhdlc_demo_setup('sfir')

8ヶ月 前 | 0

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Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

8ヶ月 前 | 0

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results of HDL streaming FFT block is not same as FFt block in dsp toolbox
dsp.HDLFFT is optimized for HDL Code generation. dsp.HDLFFT Fast Fourier transform — optimized for HDL code generation The H...

8ヶ月 前 | 0

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Potential Bugs in R2014b HDL Coder ('hdlcoder_slsysgen')
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

8ヶ月 前 | 0

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Generating higher sampling frequency
Using Oversampling Factor and Latency Strategy The Oversampling factor (HDL Coder) specifies the factor by which the FPGA clock...

8ヶ月 前 | 0

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GPU: Audio DSP
https://www.mathworks.com/help/hdlcoder/ug/running-an-audio-filter-on-live-audio-input-using-a-zynq-board.html

8ヶ月 前 | 0

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Can Matlab R2018b use the Kintex7 board from a X310 USRP and, if so, how?
https://www.mathworks.com/hardware-support/usrp.html

8ヶ月 前 | 0

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FPGA: Audio DSP
Running an Audio Filter on Live Audio Input Using a Zynq Board This example shows how to model an audio system and implement it...

8ヶ月 前 | 0

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Error while converting a sine PWM block in simulink to HDL code
See the attached example on how to generate square wave pulses at regular intervals. The waveform parameters, Amplitude, Pulse W...

8ヶ月 前 | 0

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Having issues with connecting Zynq zedboard to computer
web(fullfile(docroot, 'hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html'))

8ヶ月 前 | 0

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I want to know about the resource utilization on a FPGA when using FFT HDL code generated by HDL coder application on MATLAB.
web(fullfile(docroot, 'dsp/ref/ffthdloptimized.html?s_tid=doc_ta')) Check Performance section

8ヶ月 前 | 0

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How does it work the AXI4 Stream IIO driver?
web(fullfile(docroot, 'hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html?s_tid=doc_srchtitle')) we...

8ヶ月 前 | 0

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Best Practices for Simulink HDL Coder Development
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide HDL Coder Evaluation Referenc...

8ヶ月 前 | 0

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