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Unable to find an installed compiler.
If mex -setup points to a valid compiler; floating point to fixed point conversion should proceed without any errors. if this i...

9ヶ月前 | 0

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Is the creation of a test bench possible, without the use of the HDL coder software?
https://www.mathworks.com/products/matlab-test.html MATLAB Test provides tools for developing, executing, measuring, and managi...

9ヶ月前 | 0

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Do not undertand this error of missing license which contradicts 'license checkout statement'
... so that i can use it to generate HDL code for Microsemi Libero FPGA software ... You can try the examples in this page h...

9ヶ月前 | 0

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Please give latest version numbers of the following modules
Installing MATLAB and typing ver displays the latest version information https://www.mathworks.com/help/matlab/ref/ver.html ve...

9ヶ月前 | 0

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HDL user-defined block RAM
This usually implies generated HDL didn't meet the original MATLAB or Simulink results. Please reach out to technical support ...

9ヶ月前 | 0

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Is it possible to generate a VHDL File from a MATLAB Function that only contains one (clocked) process?
The current code style is driven by synthesis best practices. Please reach to technical support for additional customization r...

9ヶ月前 | 0

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HDL-Coder: initialization of internal VHDL-signals
All HDL Coder generated signals are fully initialized or driven with valid logic. Lack of valid drivers to signals is consid...

9ヶ月前 | 0

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How to create VHDL code of a Neural Network block created through GENSIM command ?
This example shows how to convert a neural network regression model (created using gensim) to HDL Code. https://www.mathworks...

9ヶ月前 | 0

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FPGA Synthesis and Analysis HDL coder
There are many reasons for the synthesis step to be taking a long time. If the generated HDL does not fit on the FPGA or very c...

9ヶ月前 | 0

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how can i use contiuous time integrator in hdl coder?
HDL Coder only generates code from discrete blocks. Continuous blocks are not supported. Consider using discrete time integrat...

9ヶ月前 | 0

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HDL work flow advisor for non evaluation board devices
https://www.mathworks.com/help/hdlcoder/create-a-custom-hardware-platform.html You can create your own custom reference desig...

10ヶ月前 | 0

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Compatibility of HDL coder with regression ensemble predict block and fixed point conversion
RegressionEnsemble Predict' block is currently not supported for HDL code generation. You need to build the block from first pr...

10ヶ月前 | 0

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Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL
Currently synthesis attribute specification is limited to certain blocks like product block. This capability is planned for po...

10ヶ月前 | 0

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Is it possible to generate parametrized HDL for Chart parameters?
https://www.mathworks.com/matlabcentral/answers/382489-how-are-generics-supported-in-hdl-coder Currently type generics are not ...

10ヶ月前 | 0

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The function of generating HDL code has an error with the names of blocks in the same Subsystem
" ... in the subsystem "OFDM Transmitter" will contain the subsystem "whdlOFDMTx Model". When I do generate HDL code, the name o...

10ヶ月前 | 0

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Why I get this error when working with hdl workflow?
This is an unexpected error. Can you reach out to customer support with reproduction steps? Thanks.

10ヶ月前 | 1

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Synthesize Matlab function with large input and output onto FPGA
You have a large IO design (in frames); the design needs conversion to samples. Prior to R2022b release there was no automation ...

10ヶ月前 | 0

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Can't generate Simulink model from Simulink function block
https://www.mathworks.com/help/hdlcoder/ug/hdl-optimizations-across-matlab-function-simulink-blocks.html You can convert a subs...

10ヶ月前 | 0

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How to read a matrix data from a subfunction by HDLs coder
https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples HDLCoder Design Patterns and E...

10ヶ月前 | 0

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how to configure parameters for NCO(frequency shifting or frequency correction) simulink block set based on the NCO operation has performed in the matlab script
Please find attached a sample NCO block that can generate HDL code.

10ヶ月前 | 0

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Deep Learning HDL Toolbox - Error using dnnfpga.compiler.codegenfpga Index exceeds the number of array elements. Index must not exceed 0.
This is not an expected error message. Please reach out to tech support for help and any available workaround.

10ヶ月前 | 0

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Error when converting design from Matlab Simulink to HDL
The model has an incorrect/undefined type specification. You need to use the fixdt(1,64,32) syntax. In addition, please n...

10ヶ月前 | 0

回答済み
HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing
Would you be able to share your model and HDL Coder code generation steps to reproduce the workflow?

10ヶ月前 | 0

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HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
This is not an expected error message. Please reach out to tech support with reproduction steps.

11ヶ月前 | 1

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Converting Simulink Bus with mixed datatypes to an array of doubles
Can you share your current workaround? I wonder if this block would be of help in your usecase. Bus to Vector https://www.math...

11ヶ月前 | 0

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Simulink HDL Coder & Vitis Model Composer cannot find the same Device
Model Composer library in Simulink needs Vitis workflows to generate HDL Code. https://www.xilinx.com/products/design-tools/vit...

11ヶ月前 | 0

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How to initialize Dual rate Dual port ram?
RAM System object can be used as a block in Simulink and it supports Initial Value. The HDL library browser that ships with ...

11ヶ月前 | 0

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Why did I receive an error message：ISim engine error: Failed to Load up XSI.
Please try running with Vivado 2022.1. You can see our supported software in the documentation at: https://www.mathworks.com/hel...

11ヶ月前 | 0

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HDLCoder Design Patterns and Examples
Several tutorials in this submission show how to generate HDL from MATLAB code, Simulink models, and Simscape models.

11ヶ月前 | ダウンロード 19 件 |

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Simulink port annotations do not appear with HDL definition of wire/reg
I have reported the issue to the development team. As a workaround consider right-cliking on the port, choose port propert...

11ヶ月前 | 0

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