How to create a simulink model for testbench

I'm working with HDLCoder in Simulink, my model is just an XOR, AND gates with two inputs and one output, when generating de HDL code it just generates de rtl code not the testbench, I've read that I must create another simulink model for the Testbench so that I did it but the HDL code generated has an empty architecture (Code shown below).

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY XOR_AND_tb IS
END XOR_AND_tb;


ARCHITECTURE rtl OF XOR_AND_tb IS

BEGIN
  -- All logic inside the DUT 'AND_tb' was detected to be redundant by HDL Coder. Consider connecting output ports 
  -- to the design in order to preserve logic for code generation

END rtl;

I don't know why this happens but in the HDL Coder settings the part of Testbench configuration is disabled. Any help would be appreciated. All the files of my model are attached in this answer.

[Benjamin Thompson]

Can you attach the model file and other supporting files?

[Edison Gabriel]

I've already uploaded the files of the example models that I've been using.

[Kiran Kintali]

You need to select the DUT as a subsystem or model block with the top model. The DUT needs to have a a Simulink testbench (source and sink blocks that provide stimulus and response) for the testbench panel to be enabled. Once you select a DUT, the RTL can be generated from the DUT and an RTL testbench can be generated from the stimulus and response captured from the stimulus and response.

Answer 1

[Kiran Kintali]

You need a testbench and HDL DUT subsystem to generate a valid RTL design and testbench from a Simulink model

>> makehdl('logic_model_dut_with_tb/HDL_DUT')
### Generating HDL for 'logic_model_dut_with_tb/HDL_DUT'.
### Using the config set for model logic_model_dut_with_tb for HDL code generation parameters.
### Running HDL checks on the model 'logic_model_dut_with_tb'.
### Begin compilation of the model 'logic_model_dut_with_tb'...
### Working on the model 'logic_model_dut_with_tb'...
### Working on... GenerateModel
### Begin model generation 'gm_logic_model_dut_with_tb' ....
### Copying DUT to the generated model....
### Model generation complete.
### Begin VHDL Code Generation for 'logic_model_dut_with_tb'.
### Working on logic_model_dut_with_tb/HDL_DUT as hdlsrc\logic_model_dut_with_tb\HDL_DUT.vhd.
### Code Generation for 'logic_model_dut_with_tb' completed.
### Creating HDL Code Generation Check Report HDL_DUT_report.html
### HDL check for 'logic_model_dut_with_tb' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
>> makehdltb('logic_model_dut_with_tb/HDL_DUT')
### Begin TestBench generation.
### Generating HDL TestBench for 'logic_model_dut_with_tb/HDL_DUT'.
### Begin compilation of the model 'logic_model_dut_with_tb'...
### Begin compilation of the model 'gm_logic_model_dut_with_tb'...
### Begin simulation of the model 'gm_logic_model_dut_with_tb'...

### Collecting data...
### Working on HDL_DUT_tb as hdlsrc\logic_model_dut_with_tb\HDL_DUT_tb.vhd.
### Generating package file hdlsrc\logic_model_dut_with_tb\HDL_DUT_tb_pkg.vhd.
### HDL TestBench generation complete.
 
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