Multiple IOSTANDARDs for a single HDL coder interface

My hardware designers put one of the pins i want to group together on a seperate IO bank that is 3v3 instead of 1v8.

In my HDL coder support package: Is it possible to use different IOSTANDARD for pins in one addExternalIOInterface interface?

What do I put in IOPadConstraint to define IOSTANDARD for each individual pin in the interface?

My plugin_board.m

hB.addExternalIOInterface( ...
    'InterfaceID',    'DATA_IN', ...
    'InterfaceType',  'IN', ...
    'PortName',       'DATA_IN', ...
    'PortWidth',      6, ...
   'FPGAPin',        {...
                        'L6' ,... %PMON1    1v8
                        'M6' ,... %PMON2    1v8
                        'R4' ,... %PMON3    1v8
                        'V15',... %TACHO1   3v3!!! 
                        'P1' ,... %TACHO2   1v8
                        'R5' ,... %TACHO3   1v8
                      }, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'});

Answer 1

[JT Ferrara]

You can define IOPadConstraint in one of two ways:

1. The same IOPadConstraint for all pins in the interface. For this case, use a cell array containing the constraints (as shown in your example)
2. Separate IOPadConstraint for each individual pin. For this case, use a nested cell array, where each entry is its own cell array of constraints. The number of entries must match the number of FPGA pins.

Here is an example showing a separate IOPadConstraint for each individual pin:

hB.addExternalIOInterface( ...
    'InterfaceID',    'DATA_IN', ...
    'InterfaceType',  'IN', ...
    'PortName',       'DATA_IN', ...
    'PortWidth',      6, ...
    'FPGAPin',        {...
                        'L6' ,... %PMON1    1v8
                        'M6' ,... %PMON2    1v8
                        'R4' ,... %PMON3    1v8
                        'V15',... %TACHO1   3v3!!! 
                        'P1' ,... %TACHO2   1v8
                        'R5' ,... %TACHO3   1v8
                      }, ...
    'IOPadConstraint', { ...
                        {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'}, ...
                        {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'}, ...
                        {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'}, ...
                        {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'}, ...
                        {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'}, ...
                        {'IOSTANDARD = LVCMOS18', 'PULLDOWN = TRUE'} ...
                       } ...
);

Answer 2

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ref/hdlcoder.board.addexternaliointerface.html

addExternalIOInterface('InterfaceID',interfacename,'InterfaceType',interfacetype,'PortName',portname,'PortWidth',portwidth,'FPGAPin',pins,'IOPadConstraint',constraints) 

adds an external IO interface to an hdlcoder.Board object. You can add multiple external IO interfaces to your board object.

Use this method if your board has more than one external interface, or if you want to be able to predefine FPGA pin names for mapping from the HDL Workflow Advisor.

For details about the external IO interface ports, pins, and constraints for your board, view the board documentation.