Use HDL Parameters in Cosimulation

You can configure Verilog or VHDL parameters in a cosimulation. When you use the Cosimulation Wizard to generate an HDL Cosimulation block or an hdlverifier.HDLCosimulation System object™, the Simulation Options step creates a configuration file named parameter_DUT.cfg, where DUT is the name of your HDL DUT. The configuration file includes a line for each HDL parameter, with a default value assigned. Uncomment the line for the parameter you want to configure and assign a value to override the default value.

For example, consider this generated configuration file, generated for ModelSim^® cosimulation.

# Uncomment lines below for any parameter whose default value you want to change.
# For parameters marked "N/A" (not available) the default value could not be 
# determined, but you can override in the same way.

#-G/design_top/coeff1=0
#-G/design_top/coeff2=18
#-G/design_top/coeff3=74

To change the value of coeff1 to 32, uncomment that line and assign a value of 32.

-G/design_top/coeff1=32
#-G/design_top/coeff2=18
#-G/design_top/coeff3=74

Similarly, when you cosimulate with Xcelium™, the parameters in the configuration file are created with the -gpg directive to force value assignment for generics and parameters.

-gpg "design_top.coeff1=120
#-gpg "design_top.coeff2=18
#-gpg "design_top.coeff3=74

Supported Data Types

Supported Verilog data types

• Integer — Up to 32 bit

• Real

• String — Up to 256 byte

Supported VHDL data types

• Integer

• Real

• String — Up to 256 byte

• Time

• Bit

• Boolean

• Enum

• std_logic

This feature is not supported for Vivado^® cosimulation