FPGA-in-the-Loop Simulation Workflows

You must have HDL code to perform FIL simulation. There are two FIL workflows:

• You have existing HDL code (FIL wizard).

  Note

  The FIL wizard uses any synthesizable HDL code including code automatically generated from Simulink^® models by HDL Coder™ software

• You have MATLAB^® code or a Simulink model and an HDL Coder license (HDL workflow advisor).

  Note

  When you use FIL in the Workflow Advisor, HDL Coder uses the loaded design to create the HDL code.

For either workflow, the first three steps are the same:

1. Download FPGA Board Support Package or create custom board definition files for use with FIL (see FPGA Board Customization)

2. Prepare DUT For FIL Interface Generation

3. Set Up FPGA Design Software Tools

For the next step, click the link for the workflow you are going to follow:

• If you have existing HDL code, select block or System object™ generation using the FIL wizard:

  • Block Generation with the FIL Wizard

  • System Object Generation with the FIL Wizard

• If you need the HDL workflow advisor to generate HDL code, select block or System object generation using HDL workflow advisor:

  • FIL Simulation with HDL Workflow Advisor for Simulink

  • FIL Simulation with HDL Workflow Advisor for MATLAB

Note

To use the HDL Coder HDL workflow advisor for Simulink to generate a FIL interface, you must have an HDL Coder license.