Troubleshoot Improved Adaptive Pipelining Results (Tech Preview)
R2026bNote
Improved adaptive pipelining is a tech preview in R2026b. The behavior, implementation, and interfaces might change before general release. Do not use the optimization in production designs.
To enable the improved adaptive pipelining optimization, run this command at the start of each MATLAB session:
matlab.internal.feature("GlobalAdaptivePipelining",1);To send feedback about improved adaptive pipelining, email the development team.
Issue
When you enable improved adaptive pipelining on your design, one of these outcomes can occur:
Improved adaptive pipelining does not meet the target frequency.
The estimated critical path estimation (CPE) timing does not match the timing reported by your synthesis tool.
Improved adaptive pipelining introduces more latency than expected.
Improved adaptive pipelining reports unexpected warnings on a mixed-rate design.
Uncharacterized blocks appear on the critical path.
Improved adaptive pipelining modifies a region of the design you want to leave unchanged.
The optimization does not add pipelines to fixed-point operations.
These issues occur because the improved adaptive pipelining optimization depends on device characterization data, the target frequency you specify, and the block properties on your design. When any of these inputs is incomplete or misconfigured, the results can differ from expectations.
Possible Solutions
Add Manual Pipeline Registers
Blocks or operations that are not characterized are assigned a 0 ns propagation delay. If uncharacterized blocks appear on the critical path, improved adaptive pipelining does not have enough information to insert sufficient pipeline stages.
The CPE report highlights uncharacterized blocks. Add manual pipeline registers by
setting the InputPipeline or OutputPipeline HDL block
properties on those blocks, then re-run the makehdl function. In
subsequent iterations, improved adaptive pipelining accounts for the manual
pipelines.
Adding manual pipeline registers breaks the critical path directly, so this solution works whether or not the CPE report characterizes the operation. Because the fix does not depend on characterization data, it provides an immediate improvement without a long characterization step.
Regenerate the Timing Database
If the design does not meet the target frequency, improved adaptive pipelining reached the maximum achievable frequency for your design. Check the CPE report for the operation that limits the critical path.
If the characterized timing appears systematically inaccurate for your device,
regenerate the timing database by using the genhdltdb
Set the TargetFrequency Model Configuration Parameter Higher Than Your Required Frequency
Critical path estimation captures post-map timing only and does not model routing delay. Post-synthesis timing includes routing and can be lower than the CPE estimate.
To provide a margin for the CPE, set the TargetFrequency model
configuration parameter higher than your actual frequency requirement. Improved adaptive
pipelining then inserts additional pipeline stages.
Verify the Value of the TargetFrequency Model Configuration Parameter
Improved adaptive pipelining resizes the pipeline depth to meet the target frequency. A
higher TargetFrequency model configuration parameter value results in
more pipeline stages.
Verify that TargetFrequency is not higher than necessary. For
operations that map to a DSP, such as a Gain or Product block,
improved adaptive pipelining inserts a maximum of 20 pipeline stages close to that block.
However, a Gain or Product block is a single operation in a
larger design. Improved adaptive pipelining does not otherwise limit the amount of latency
that it can introduce in the data path when it adds pipeline registers to meet the target
frequency.
Disable the AdaptivePipelining HDL Block Property on Optimized Subsystems
Because critical path estimation interprets every path as raw combinational delay regardless of the clock rate, it can misidentify multicycle paths as critical.
Only use improved adaptive pipelining on specific rate regions. Set the
AdaptivePipelining HDL block property to off on
subsystems that are already optimized for their clock rate.
Exclude a Region from Improved Adaptive Pipelining
Improved adaptive pipelining inserts registers across the entire DUT subsystem by
default. To leave a region unchanged, set the AdaptivePipelining HDL block property of the Subsystem block to off.
Data Type Conversions Between DSP-Mapped Multipliers
Data type conversion between two multipliers that map to DSP primitives limits register-packing. The conversion can come from an explicit Data Type Conversion block or implicitly from block settings on either multiplier. Block settings that introduce a type conversion include:
Selecting the Saturate on integer overflow block parameter
Setting the Integer rounding mode block parameter to any value other than
FloorSetting the Output data type block parameter to a width that differs from the full-precision product width
HDL Coder generates combinational cast logic between the two multiplier stages. Adaptive pipelining places a fabric register after that combinational logic, and the synthesis tool does not absorb this register into either adjacent DSP primitive.
When possible, keep inherited widths, wrap-around overflow, and floor rounding between DSP-mapped multipliers, or place any required type conversion outside the DSP-mapped multiplier chain.
Set the LatencyStrategy HDL Block Property to Auto
Fixed-point iterative-algorithm blocks use predefined pipeline depths when the
LatencyStrategy HDL block property is set to a value other than
Auto. The LatencyStrategy property applies to these
blocks and HDL architectures:
Sqrt blocks where the Architecture HDL block property is
SqrtFunctionDivide and Reciprocal blocks where the Architecture HDL block property is
ShiftAddTrigonometric Function blocks where the Architecture HDL block property is
Trigonometric, the Function block parameter issin,cos,sincos,cos+jsin, oratan2, and the Approximation method block parameter isCORDICComplex to Magnitude-Angle blocks where the Approximation method block parameter is
CORDIC
For these blocks, set the LatencyStrategy HDL block property to
Auto. Improved adaptive pipelining then sizes the pipeline stages of
the fixed-point operations based on critical path analysis for the target device and
frequency.
hdlset_param(block, "LatencyStrategy", "Auto");
Disable the DistributedPipelining HDL Block Property in Designs with Feedback Loops
In designs with feedback loops, enabling the DistributedPipelining
HDL block property with improved adaptive pipelining can obscure the design delay that
improved adaptive pipelining uses to insert registers, leading to excessive latency without
meeting the target frequency. Feed-forward paths that combine both optimizations are
supported.
Use Improved Adaptive Pipelining Instead of the hdlcoder.optimizeDesign Function
Use improved adaptive pipelining instead of the hdlcoder.optimizeDesign
