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Introduction to Stateflow HDL Code Generation

Stateflow® charts describe complex system behavior by using hierarchical finite state machine (FSM) theory, flow diagram notation, and state transition diagrams.

You can use a chart to model a finite state machine or complex control algorithm for an ASIC or FPGA. When the model meets the design requirements, you then generate VHDL®, Verilog® or SystemVerilog code that implements the design. You can simulate and synthesize the generated HDL code by using industry-standard tools, and then map your system designs on FPGAs and ASICs. For more information on how to generate HDL code for finite state machines, see Generate HDL for Mealy and Moore Finite State Machines.

Generate HDL Code from Stateflow Charts

This example uses:

Open Live Script

This example shows how to generate HDL code for a subsystem that includes Stateflow charts.

Open Model

The model hdlcodercfir implements a pipelined, configurable, and symmetric FIR filter.

To open the model, run this command in the MATLAB Command Window:

open_system("hdlcodercfir");

A Stateflow chart inside the subsystem controls the resource sharing. To open this subsystem, enter:

subsystem="hdlcodercfir/cfir_system";
open_system(subsystem);

Configure Chart Properties

1. To open the Stateflow chart, double-click the fsm chart or enter:

open_system("hdlcodercfir/cfir_system/fsm");

2. On the Simulink Toolstrip, on the Modeling tab, click Chart Properties. To generate HDL code, the Action Language property must be C and the State Machine Type property must be Classic.

3. Enable the Execute (enter) chart at initialization property to update the chart immediately after chart initialization. You cannot perform arithmetic in initialization actions because reset actions are unable to manage the latency associated with combinatorial logic. For more information, see Execution of a Chart at Initialization (Stateflow).

4. Select the Initialize Outputs Every Time Chart Wakes Up property. If you clear this property, the generated HDL code includes an additional register for the state machine output values.

Generate HDL Code for Subsystem

Before you generate HDL code, enable the traceability in the generated code. When you enable traceability support, the code generator produces code with bi-directional traveability. You can view the generated code in the HDL Code pane or in the HTML code generation report. You can use the traceable generated code to verify that the generated code meets the design requirements.

1. To enable the traceability in the generated code, click Settings. In the HDL Code Genereation > Report pane, select the Generate traceability report parameter. By default, the code generator uses the line-level style to generate the traceability. You can customize the style by changing the Traceability style parameter.

2. Click Apply and then OK. Alternatively, enter:

hdlset_param("hdlcodercfir","Traceability","On");

3. To generate HDL code for the subsystem that contains the Stateflow chart, on the HDL Code tab, click Generate HDL Code. Alternatively, enter:

workingdir = tempname;
makehdl(subsystem,"TargetDirectory",workingdir);
### Working on the model hdlcodercfir
### Generating HDL for hdlcodercfir/cfir_system
### Using the config set for model hdlcodercfir for HDL code generation parameters.
### Running HDL checks on the model 'hdlcodercfir'.
### Begin compilation of the model 'hdlcodercfir'...
### Working on the model 'hdlcodercfir'...
### Working on... GenerateModel
### Begin model generation 'gm_hdlcodercfir'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/gm_hdlcodercfir.slx
### Begin VHDL Code Generation for 'hdlcodercfir'.
### Working on... Traceability
### Working on hdlcodercfir/cfir_system/datapath/acc as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/acc.vhd.
### Working on hdlcodercfir/cfir_system/datapath/mult as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/mult.vhd.
### Working on hdlcodercfir/cfir_system/datapath/pre_add as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/pre_add.vhd.
### Working on hdlcodercfir/cfir_system/datapath as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/datapath.vhd.
### Working on hdlcodercfir/cfir_system/fsm as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/fsm.vhd.
### Working on hdlcodercfir/cfir_system as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/cfir_system.vhd.
### Generating package file /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/cfir_system_pkg.vhd.
### Code Generation for 'hdlcodercfir' completed.
### Generating HTML files for code generation report at hdlcodercfir_codegen_rpt.html
### Creating HDL Code Generation Check Report file:///tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/cfir_system_report.html
### HDL check for 'hdlcodercfir' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

4. View the generated code in HTML report or the HDL Code pane. The HTML report offers other reports that provide insights about the generated code.

You can use the HDL Code pane to navigate and trace the generated code for corresponding Stateflow elements. For example, when you select the idle state in the Stateflow chart, HDL Coder highlights the generated code in the HDL Code pane.

Generate Test Bench for Subsystem

To generate a test bench for the cfir_system subsystem, on the HDL Code tab, click Generate Testbench. Alternatively, enter:

makehdltb("hdlcodercfir/cfir_system");
### Begin TestBench generation.
### Generating HDL TestBench for 'hdlcodercfir/cfir_system'.
### Begin compilation of the model 'hdlcodercfir'...
### Begin compilation of the model 'gm_hdlcodercfir'...
### Begin simulation of the model 'gm_hdlcodercfir'...

### Collecting data...
### Generating test bench data file: /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/coeff_address.dat.
### Generating test bench data file: /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/load_coeff.dat.
### Generating test bench data file: /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/input_data.dat.
### Generating test bench data file: /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/output_data_expected.dat.
### Working on cfir_system_tb as /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/cfir_system_tb.vhd.
### Generating package file /tmp/Bdoc24b_2855429_943983/tpe845b9d4_399a_4c13_9832_e0a2916a7ccc/hdlcodercfir/cfir_system_tb_pkg.vhd.
### HDL TestBench generation complete.

Latency of Stateflow Blocks

When the optimizations or block implementations introduce latency in a model, the total latency associated with the Stateflow block is summed up at the output of the block. You can view the detailed information on blocks that introduce latencies due to optimization requests or the implementation of certain block architectures in the Delay Balancing optimization report. For more information, see Delay Balancing.

For example, the Stateflow Chart shown in figure has DistributedPipelining enabled and OutputPipeline is set to 8. Due to these HDL optimizations, HDL Coder™ introduces 8 cycles of latency to the block. To view detailed information on latency introduced due to the optimizations, generate the optimization report for your model and view the Delay Balancing report.

Optimization on Stateflow Block. Latency of 8 cycles in generated model.

Optimizations for Stateflow Blocks

You can apply these optimizations to Stateflow blocks to optimize the generated code for speed and area.

Limitations

HDL code generation does not support Stateflow blocks that contain messages.

Location of Charts in the Model

To generate HDL code from a chart, the chart must be part of a Simulink® subsystem. If the chart for which you want to generate code is at the root level of your model, embed the chart in a subsystem and connect the relevant signals to the subsystem inputs and outputs.

Data Types

The code generator supports these MATLAB® data types in charts:

  • Signed and unsigned integer

  • Fixed point

  • Boolean

  • Enumeration

Note

Multidimensional arrays are not supported for data types assigned to ports. Port data types must be either scalar or vector.

If you use single and double data types, HDL Coder generates real data types in the HDL code. You can simulate and verify the code by using third-party simulators such as ModelSim™.

Real types are not synthesizable on the target FPGA device. HDL code generation does not support Stateflow charts in native floating point mode. To generate synthesizable HDL code for floating-point data types, develop an algorithm by using MATLAB Function blocks or see Simulink Blocks Supported by Using Native Floating Point.

Imported Code

Charts must be entirely self-contained. These restrictions apply:

  • Do not call MATLAB functions other than min or max.

  • Do not use MATLAB System objects in a Chart block.

  • Do not use MATLAB workspace data.

  • Do not call C math functions. HDL does not have a counterpart to the C math library.

  • If the Enable C-bit operations property is cleared, do not use the exponentiation operator (^). The exponentiation operator uses C math library function pow.

  • Do not include custom code. The code generator ignores information on the Simulation Target > Custom Code pane in the Configuration Parameters dialog box.

  • Do not use Data Store Memory blocks to share data between charts. HDL Coder does not map global data to HDL because HDL does not support global data.

Vector of Tunable Parameters

HDL code generation does not support using vectors of tunable parameters as data types for Chart blocks.

Input and Output Events

HDL Coder supports the use of input and output events with Stateflow charts, with these constraints:

  • You can define and use only one input event per Stateflow chart. There is no restriction on the number of output events.

  • The code generator does not support HDL code generation for charts that have a single input event and nonzero initial values on the output ports.

  • All input and output events must be edge-triggered.

For detailed information about input and output events, see Activate a Stateflow Chart by Sending Input Events (Stateflow) and Activate a Simulink Block by Sending Output Events (Stateflow).

Messages

Stateflow messages are not supported for HDL code generation.

Loops

Other than for-loops, do not explicitly use loops in a chart intended for HDL code generation. Observe these restrictions for for-loops:

  • The data type of the loop counter variable must be int32.

  • HDL Coder supports only constant-bounded loops.

The for-loop example, sf_for, shows a design pattern for a for-loop that uses a graphical function.

Additional Limitations

Because HDL does not support some features of general-purpose sequential programming language, Stateflow charts must meet these additional restrictions:

  • You must make separate copies for each instance of an atomic subchart. HDL Coder does not support code generation for atomic subcharts. For more information, see Convert an Atomic Subchart to a Normal Subchart (Stateflow).

  • Do not generate HDL code for Simulink Function blocks.

  • Do not define local events in a chart from which HDL code is generated.

  • Do not use these implicit events:

    • enter

    • exit

    • change

    You can use these implicit events:

    • wakeup

    • tick

  • If the base events are limited to these types of implicit events, you can use temporal logic.

  • Do not use recursion through graphical functions. HDL Coder does not support recursion.

  • Avoid unstructured code. Although charts allow unstructured code in the form of transition flow diagrams and graphical functions, this usage results in goto statements and multiple function return statements. HDL does not support goto statements or multiple function return statements.

  • If the Initialize Outputs Every Time Chart Wakes Up chart option is cleared, do not read from output ports.

  • Do not use Data Store Memory objects.

  • Do not use pointer (&) or indirection (*) operators. See Pointer and Address Operations (Stateflow).

  • If a chart returns a run-time overflow error during simulation, it is possible to disable data range error checking and generate HDL code for the chart. In this case, some results obtained from the generated HDL code may not be bit-true to the results from the simulation. The recommended practice is to enable the overflow checking and eliminate overflow conditions in the model.

See Also

(Stateflow) | (Stateflow) | (Stateflow)

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