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Guidelines for Clock and Reset Signals

In the Simulink® modeling environment, You do not create global signals such as clock, reset, and clock enable. These signals are created when you generate HDL code for your model. You can specify the clock cycle by using the sample time in Simulink.

If your model is single rate, it means all blocks operate at the same sample time. The synthesis tools infer that the registers or Delay blocks you add to your model run at the clock rate. For the synthesis tools, data propagates from the source register to the destination register in one clock cycle.

You can follow these guidelines to learn about generating clock signals in the HDL code. Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.

Use Global Oversampling to Create Frequency-Divided Clock

Guideline ID

1.4.1

Severity

Informative

Description

You can assign a frequency-divided clock rate for HDL code generation to be a multiple of the Simulink base sample rate. For example, if the Simulink base rate is 1 MHz and you want the clock frequency of your target hardware to run at 50 MHz, you can assign an Oversampling factor of 50. You specify the Oversampling factor in the HDL Code Generation > Global Settings pane of the Configuration Parameters dialog box. To learn more, see Generate a Global Oversampling Clock.

Create Multirate Model with Integer Clock Multiples by Clock Division

Guideline ID

1.4.2

Severity

Mandatory

Description

You can generate a multirate model by using clock-rate division or by using clock multiples. For a multirate model, the fastest sample time in your Simulink™ model corresponds to the master clock rate. A timing controller entity is created to control the clocking for blocks operating at slower sample rates. Clock enable signals that have the necessary rate and phase information control the clocking for these blocks in your design.

Multirate models are created when you use certain blocks in your Simulink™ model, specify certain block architectures, or use operations such as resource sharing. For example, these block-architecture combinations generate a multirate model:

  • Divide block with Newton-Raphson implementation.

  • Reciprocal block with ReciprocalSqrtBasedNewton implementation.

  • Sum of Elements and Product of Elements blocks with Cascade architecture.

  • Sqrt with SqrtBasedNewton and Reciprocal Sqrt with ReciprocalRsqrtBasedNewton implementation.

In addition, to model multirate designs in Simulink™, use these blocks:

  • In the Simulink > Signal Attributes Library, use the Rate Transition block.

  • In the DSP System Toolbox > Signal Operations Library, you can use Upsample, Downsample, and Repeat blocks.

  • In the HDL Coder > HDL RAMs Library, use the HDL FIFO block.

This model illustrates how to create a multirate design by using a Rate Transition block.

load_system('hdlcoder_multiclock')
set_param('hdlcoder_multiclock','SimulationCommand','Update')
open_system('hdlcoder_multiclock')

The different colors in the model indicate that the model is multirate and has a faster rate D1 and a slower rate D2. To see the Rate Transition block that produces the different sample rates, double-click the DUT Subsystem.

open_system('hdlcoder_multiclock/DUT')

To see the sample times in your model, run this command:

ts = Simulink.BlockDiagram.getSampleTimes('hdlcoder_multiclock');
sampletime_D1 = ts(1)
sampletime_D2 = ts(2)
sampletime_D1 = 

  SampleTime with properties:

                   Value: [1.0000e-03 0]
             Description: 'Discrete 1'
           ColorRGBValue: [0.9000 0 0]
              Annotation: 'D1'
              OwnerBlock: []
    ComponentSampleTimes: [0x0 Simulink.SampleTime]


sampletime_D2 = 

  SampleTime with properties:

                   Value: [0.0030 0]
             Description: 'Discrete 2'
           ColorRGBValue: [0 0.8200 0]
              Annotation: 'D2'
              OwnerBlock: []
    ComponentSampleTimes: [0x0 Simulink.SampleTime]

When you use a Rate Transition block in your model for multirate design, select the block parameters Ensure data integrity during data transfer and Ensure deterministic data transfer (maximum delay). Make sure the output sample rate is an integer multiple of the input sample rate.

For a multirate design, you can generate a single clock signal or multiple clock signals to control the clocking to blocks that operate at various sample rates. To specify this setting, in the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings pane, specify the Clock inputs setting.

By default, Clock inputs is specified as single. A single clock is generated to control the clocking for all registers or Delay blocks in your model. The timing controller enable signals control the clocking to various blocks in your design. This mode can increase the power dissipation as a single, fastest clock is connected to all registers in your design.

If you specify Clock inputs as multiple, a clock signal is generated for each sample rate in your design. However, this mode requires you to connect each of the clock, clock enable, and reset ports externally. This mode reduces power as the HDL design contains registers connected to slower clock signals. For more information, see Using Multiple Clocks in HDL Coder.

Use Dual Rate Dual Port RAM for Noninteger Multiple Sample Times

Guideline ID

1.4.3

Severity

Mandatory

Description

When you use Rate Transition, Upsample, or Downsample blocks to create multirate models, the clock rates must be integer multiples of the base rate. To create a multirate model with clocks that are noninteger multiples, use a Dual Rate Dual Port RAM block. For integer clock multiplies, you can use the HDL FIFO or the Dual Rate Dual Port RAM block.

This model illustrates how you can create noninteger multiples of sample rates.

load_system('hdlcoder_dual_rate_dual_port_RAM')
set_param('hdlcoder_dual_rate_dual_port_RAM','SimulationCommand','Update')
open_system('hdlcoder_dual_rate_dual_port_RAM/DUT')

You cannot generate HDL code for this model because the Rate Transition blocks have the block parameter Ensure data integrity during data transfer cleared. To learn how you can manage address control when you use the RAM block, see Design considerations for RAM block access.

Asynchronous Clock Modeling in HDL Coder

Guideline ID

1.4.4

Severity

Recommended

Description

Most FPGA designs must have more than one clock domain with multiple parts of the design operating at various frequencies. You can model the various clock domains in Simulink™ by using a pass-through implementation for transitioning between different sample rates. These sample rates correspond to the clock rates on the FPGA device.

For an example, open the model hdlcoder_multi_clock_domain and then open the DUT Subsystem.

load_system('hdlcoder_multi_clock_domain')
set_param('hdlcoder_multi_clock_domain', 'SimulationCommand', 'Update')
open_system('hdlcoder_multi_clock_domain/DUT')

You see a BlackBox Subsystem that contains a DocBlock, which is a text file that corresponds to the Verilog code for a passthrough implementation. You can open the DocBlock to see the Verilog code. You see that the output of this Subsystem operates at a different sample rate or is in a clock domain that is different from the sample rate at the input of the Subsystem. The Subsystem also contains a commented out path that contains the VHDL equivalent of the passthrough implementation. To generate VHDL code, uncomment this path and comment out the path that contains the Verilog BlackBox implementation.

To generate Verilog code for this model, run this command:

makehdl('hdlcoder_multi_clock_domain/DUT')

In the generated Verilog header file, you see the different clock domains in the model.

// -------------------------------------------------------------
// 
// File Name: hdlsrc\hdlcoder_multi_clock_domain\DUT.v
// Created: 2018-10-05 11:30:21
// 
// Generated by MATLAB 9.6 and HDL Coder 3.13
// 
// 
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 1.30208e-12
// Target subsystem base rate: 2.65428e-12
// 
// 
// Clock      Domain  Description
// -- -------------------------------------------------------------
// clk_1_3072 1       3072x slower than base rate clock
// clk_1_3125 2       3125x slower than base rate clock
// -- -------------------------------------------------------------
// 
// Output Signal                 Clock      Domain  Sample Time
// -- -------------------------------------------------------------
// Output1                       (no clock) 0       4.06901e-09
// -- -------------------------------------------------------------
// 
// -------------------------------------------------------------

Use Global Reset Type Setting Based on Target Hardware

Guideline ID

1.4.5

Severity

Recommended

Description

Matching the reset type to the FPGA architecture can improve resource utilization and the speed at which your design runs on the target hardware. To control this setting, in the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings settings, specify the Reset type.

When you target Xilinx® devices, set Reset type to Synchronous. For Intel® or Altera® devices, set Reset type to Asynchronous.

To make sure that you use the correct reset type for the hardware that you are targeting, in the HDL Code Advisor, run the model check Check for global reset setting for Xilinx and Altera devices.

Note

Some Intel devices recommend using synchronous reset. For recommended reset settings, see the Intel or Xilinx documentation for that device.

See Also

Functions

Simulink Configuration Parameters

Related Topics