Catapult® Synthesis is a high-level C++ and SystemC synthesis tool for digital IC designers who need to deliver optimal ASIC or FPGA implementations with aggressive time-to-market schedules.
Traditional hardware design methods that require handwritten RTL (VHDL® or Verilog®) are extremely time-consuming and error-prone for complex designs. Catapult empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult C generates RTL targeting ASIC or FPGA technologies, reducing the time to verified and production-quality hardware.
Catapult offers a verification interface that enables the use of Catapult by design teams using MATLAB® or Simulink® as their system modeling environment.
With Catapult, users describe the hardware design using ANSI C++ and SystemC. Catapult allows users to perform architectural space exploration to meet power, performance, and area constraints. At any time during this design process, the designer can export the model to MATLAB and Simulink for system-level verification.
Catapult generates MATLAB MEX-functions and Simulink S-function wrappers from synthesizable ANSI C++ and SystemC models. These models allow MATLAB and Simulink users to verify the synthesizable hardware implementation in the context of system-level models. Catapult can launch a MATLAB session and load the generated model into MATLAB or Simulink.
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