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Balance clock-rate pipelined DUT output ports

Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs

Since R2022b

Model Configuration Pane: Optimization / Pipelining

Description

Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs. Apply this option when interfacing your logic with a valid signal interface to align the output of the logic path and valid signal path.

Dependencies

To enable this parameter, select the Allow clock-rate pipelining of DUT output ports check box.

Settings

Off (default) | On
On

Synchronize the DUT outputs.

Off

Produce the DUT outputs as soon as possible, without synchronization.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the BalanceClockRateOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        'BalanceClockRateOutputPorts','on')

  • When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

    hdlset_param('sfir_fixed','BalanceClockRateOutputPorts','on')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: BalanceClockRateOutputPorts
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Version History

Introduced in R2022b

See Also

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