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Use Target Hardware Instruction Set Extensions to Generate SIMD Code from Simulink Blocks for Apple silicon

Note

This workflow requires an Embedded Coder® license.

This topic shows how to generate single instruction, multiple data (SIMD) code from Simulink® blocks for Apple silicon processors by using the model configuration parameter Leverage target hardware instruction set extensions.

  1. Open the Embedded Coder app from the Apps gallery in the Simulink model toolstrip.

  2. In the C Code tab, select Settings > Hardware Implementation.

  3. Set the Device vendor (Simulink) parameter to Apple.

  4. Set the Device type (Simulink) parameter to ARM64.

  5. On the Code Generation > Optimization pane, from the Leverage target hardware instruction set extensions (Simulink Coder) list, select the instruction set extension supported by your processor. For this example, select Neon v7.

  6. Optionally, select the Optimize reductions (Simulink Coder) parameter to generate SIMD code for reduction operations or the FMA (Simulink Coder) parameter to generate SIMD code for fused multiply-add operations.

  7. On the Code Generation > Interface pane, under Software environment, set Code replacement libraries to None, and clear Support non-finite numbers.

  8. Depending on the blocks you use in your model, you might have to change additional block-level settings to generate SIMD code using this workflow. For more information on these settings, see the Extended Capabilities : C/C++ Code Generation sections in the respective block reference pages.

  9. Generate code from the model.

The SIMD instructions are the intrinsic functions that start with the identifier v in the generated code. These functions process multiple data in a single iteration of the loop because the loop increments by four for single data types and by two for double data types. For models that process more data and are computationally more intensive, the SIMD instructions can significantly speed up the code execution time.

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