Overview
Learn how to use HDL Coder optimization and design techniques to meet your target-specific speed and area goals. HDL Coder offers techniques that span from automatic to fully-controlled, and all of them allow for rapid exploration of implementation options. This webinar will explain these options and their associated benefits and tradeoffs, including verification considerations, and will discuss techniques specific to FPGA and ASIC targeting. All of these techniques will be demonstrated using the pulse detection design from the HDL Self-Guided Tutorial.
Highlights
- Workflow options from rapid estimation to running full synthesis and implementation
- Optimizing for speed
- Latency vs throughput vs clock frequency
- Pipelining techniques
- Vector processing
- Multiplier mapping
- Optimizing for area
- Resource sharing
- RAM mapping
- Loop streaming of vector operations
About the Presenter
Jack Erickson is responsible for technical product marketing for FPGA, ASIC and SoC development at MathWorks. Prior to joining MathWorks, he spent over 20 years at Cadence Design Systems, Inc., as an applications engineer and in product marketing for simulation, RTL synthesis, and high-level synthesis. He has a BSEE from Tufts University and an MBA from Worcester Polytechnic Institute.
