Check for root Inports with missing properties

mathworks.hism.hisl_0024

Dependencies: Simulink^® Check™

Usage: High-Integrity System Modeling

Guideline: hisl_0024: Inport interface definition

Description

This check identifies root-level Inport blocks for missing or inherited sample times, data types, or port dimensions.

• Root-level Inport blocks with missing or inherited sample times, data types, or port dimensions for Simulink models.

  Using root model Inport blocks that do not have defined sample time, data types or port dimensions can lead to undesired simulation results. Simulink back-propagates dimensions, sample times, and data types from downstream blocks unless you explicitly assign these values. You can specify Inport block properties with block parameters or Simulink signal objects that explicitly resolve to the connected signal lines.

• Root-level input ports with missing or inherited data types or port dimensions for architecture models.

When you run the check, a results table provides links to Inport blocks and Simulink signal objects that do not pass, along with conditions triggering the warning.

Recommended Actions and Results

Review the violations that are flagged by the check and the recommended action for fixing the issue. After applying the changes, save the model and rerun the check analysis.

Modeling Condition	Recommended Action
Model contains Inport blocks with inherited port dimensions.	For the Inport blocks and Simulink signal objects listed in the results, specify port dimensions.
Model contains Inport blocks with inherited data types.	For the Inport blocks and Simulink signal objects listed in the results, specify data types.
Model contains Inport blocks with inherited sample times.	For the Inport blocks and Simulink signal objects listed in the results, specify sample times. The sample times for root Inports with bus type must match the sample times specified at the leaf elements of the bus object.
Model contains Inport block signal names that implicitly resolve to Simulink signal objects in the base workspace, model workspace, or Simulink data dictionary.	For the Simulink signal objects listed in the results, in the Signal Properties dialog box, select Signal name must resolve to Simulink signal object. To set this option programmatically, set the port parameter MustResolveToSignalObject to "on".
One or more input ports of an architecture model do not have a data interface assigned to it.	Assign data interfaces to input ports listed in the results.

Capabilities and Limitations

• Does not report warnings when input ports use inherited sample time if the configuration parameter Solver > Periodic sample time constraint is set to Ensure sample time independent

• For export-function models, inherited sample time is not flagged

• Does not run on library models

• Does not require model compilation

• Does not support exclusion in architecture models

• Does not analyze the content of library-linked blocks

• Does not analyze the content in masked subsystems

• Allows exclusions of blocks and charts

• Supports edit-time checking

• Supports bus element ports

  Note

  Implicit resolution to a Simulink signal object is not applicable for signals connected to bus element ports.

Version History

Introduced in R2018b