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specifyOutput

Assign HDL output ports to cosimulation block or System object

Since R2022b

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    Syntax

    specifyOutput(cosimConfigObj,name)
    specifyOutput(__ ,Name=Value)
    specifyOutput(__ ,name,[])

    Description

    specifyOutput(cosimConfigObj,name) explicitly maps the HDL port named name as an output in the generated block or System object™. The attributes for the output inherit default values from the 'default_output_definition' row of the OutputDataPorts table.

    specifyOutput(__ ,Name=Value) sets properties using one or more name-value arguments in addition to the input arguments in the previous syntax. Unspecified arguments inherit the value from 'default_output_definition'.

    To change the default output attributes, specify values for the 'default_output_definition'.

    specifyOutput(__ ,name,[]) clears the definition for the output port (or ports) specified in name. For example: specifyOutput(c,out1,[]) clears the definition for the output named out1 in the OutputDataPorts table.

    Input Arguments

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    Cosimulation configuration, specified as a cosimulationConfiguration object.

    Name of the HDL port to map as an output in the generated HDL Cosimulation block or hdlverifier.HDLCosimulation System object, specified as a string or a character vector. For multiple outputs, specify a cell array of port names.

    Example: name='data_out'

    Example: name={'out1','out2','out3'}

    Data Types: char | string

    Name-Value Arguments

    Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

    Example: specifyOutput(c, {'dout1','dout2'},DataType='Fixedpoint',Signed=true,FractionLength=10); creates two output ports with the default SampleTime, with signed Fixedpoint data type and fraction length of 10.

    Time interval between consecutive samples applied to an output port, specified in seconds.

    • Specify a nonnegative numeric value as the output port sample time

    • Specify -1 for Simulink® workflows to inherit the sample time via back propagation in the Simulink model.

    Simulink reads a value from the associated HDL simulator signal at the sample rate specified here.

    In general, Simulink handles port sample periods as follows:

    • If you connect an input port to a signal that has an explicit sample period, based on forward propagation, Simulink applies that rate to the port.

    • If you connect an input port to a signal that does not have an explicit sample period, Simulink assigns a sample period that is equal to the least common multiple (LCM) of all identified input port sample periods in the model.

    You must specify an explicit sample time for each output port.

    The HDL time corresponding to the Simulink sample time hits depends on the TimeScale setting. See Simulation Timescales for more information.

    Data type of the output signal, specified as 'Fixedpoint', 'Double', 'Single', or 'Inherit' (for Simulink workflow only).

    When building a Simulink workflow, you can select 'inherit' to automatically determine the data type. The HDL Cosimulation block checks that the inherited word length matches the word length queried from the HDL simulator. If they do not match, Simulink generates an error message. For example, if you connect a Signal Specification block to an output, Inherit forces the data type specified by the Signal Specification block onto the output port.

    If Simulink cannot determine the data type of the signal connected to the output port, it queries the HDL simulator for the data type of the port. For example, if the HDL simulator returns the VHDL® data type STD_LOGIC_VECTOR for a signal of size N bits, the data type ufixN is forced on the output port. The implicit fraction length is 0.

    You can also assign an explicit data type, with optional fraction length. By explicitly assigning a data type, you can force fixed-point data types on output ports of the HDL Cosimulation block or system object. For example, for an 8-bit output port, setting Signed to true and setting FractionLength to 5 forces the data type to sfix8_En5. The width is always inherited from the HDL simulator.

    Example: DataType='Fixedpoint'

    Sign of the outputs, specified as true (signed) or false (unsigned).

    Example: true – All outputs have a signed value.

    Output fraction length, in bits, specified as an integer.

    If you do not specify this property, the fraction length inherits the value from 'default_output_definition'.

    Example: 10 — The specified output has a fraction length of 10 bits.

    Version History

    Introduced in R2022b

    See Also

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