coder.HdlConfig

HDL codegen configuration object

Description

A coder.HdlConfig object contains the configuration parameters that the HDL codegen function requires to generate HDL code. To pass this object to the codegen function, use the -config option.

Creation

Syntax

hdlcfg = coder.config("hdl")

Description

hdlcfg = coder.config("hdl") creates a coder.HdlConfig object for HDL code generation.

Properties

Basic

AdaptivePipelining — Insert adaptive pipeline registers in your design

false (default) | true

Enable adaptive pipelining to insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.

When you specify this parameter, specify the Synthesis Tool in the Select Code Generation Target task. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.

Data Types: logical

AdderSharingMinimumBitwidth — Minimum bit width for shared adders

0 (default) | integer greater than or equal to 2

Minimum bit width for shared adders, specified as a positive integer.

If ShareAdders is true and ResourceSharing is greater than 1, share adders only if adder bit width is greater than or equal to AdderSharingMinimumBitwidth.

Data Types: int32

ClockEdge — Active clock edge

'Rising' (default) | 'Falling' | "Rising" | "Falling"

Specify active clock edge.

Data Types: char | string

DistributedPipelining — Distributed pipelining optimization

false (default) | true

Enable to distribute pipeline registers. When enabled, HDL Coder™ moves registers within your design to reduce critical path.

Data Types: logical

DistributedPipeliningPriority — Priority for distributed pipelining algorithm

'NumericalIntegrity' (default) | 'Performance' | "NumericalIntegrity" | "Performance"

DistributedPipeliningPriority Value	Description
NumericalIntegrity (default)	Prioritize numerical integrity when distributing pipeline registers. This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown.
Performance	Prioritize performance over numerical integrity. Use this option if your design requires a higher clock frequency and the MATLAB® behavior does not need to strictly match the generated code behavior. This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design’s functional equivalence to the original design is unknown.

Data Types: char | string

GenerateHDLTestBench — Generate an HDL test bench

false (default) | true

Generate an HDL test bench.

Data Types: logical

HDLCodingStandard — HDL coding standard to follow

'None' (default) | 'Industry' | "None" | "Industry"

HDL coding standard to follow when generating code. Generates a compliance report showing errors, warnings, and messages.

Data Types: char | string

HDLCodingStandardCustomizations — HDL coding standard rules and report customizations

none (default) | HDL coding standard customization object

HDL coding standard rules and report customizations, specified by using HDL Coding Standard Customization Properties. For more information, see HDL Coding Standard Customization Properties. If you want to customize the coding standard rules and report, you must set HDLCodingStandard to "Industry".

HDLLintTool — HDL lint tool script

'None' (default) | 'AscentLint' | 'Leda' | 'SpyGlass' | 'Custom' | "None" | "AscentLint" | "Leda" | "SpyGlass" | "Custom"

HDL lint tool script to generate.

Data Types: char | string

HDLLintInit — HDL lint script initialization name

'' (default)

HDL lint script initialization name, specified as a string scalar or character vector.

Data Types: char | string

HDLLintCmd — HDL lint script command

'' (default)

If you set HDLLintTool to Custom, you must use %s as a placeholder for the HDL file name in the generated Tcl script. Specify HDLLintCmd as a string scalar or character vector by using this format:

custom_lint_tool_command -option1 -option2 %s

Data Types: char | string

HDLLintTerm — HDL lint script termination name

'' (default)

HDL lint script termination name.

Data Types: char | string

InitializeBlockRAM — Initialize block RAM

true (default) | false

Specify whether to initialize block RAM to 0 for simulation.

Data Types: logical

InlineConfigurations — Include inline configurations in generated VHDL code

true (default) | false

Specify whether to include inline configurations in generated VHDL code.

When true, include VHDL configurations in files that instantiate a component.

When false, suppress the generation of configurations and require user-supplied external configurations. Set to false if you are creating your own VHDL configuration files.

Data Types: logical

InputPipeline — Number of input pipeline register stages

0 (default) | integer greater than 0

Specify the number of input pipeline register stages. When DistributedPipelining is enabled, these registers can be distributed through the design.

Data Types: int32

InstantiateFunctions — Generate instantiable HDL code modules

false (default) | true

Specify whether to generate instantiable HDL code modules from functions.

Data Types: logical

LoopOptimization — Loop optimization

'LoopNone' (default) | 'StreamLoops' | 'UnrollLoops' | "LoopNone" | "StreamLoops" | "UnrollLoops"

Loop optimization in generated code. See Optimize MATLAB Loops.

LoopOptimization Value	Description
LoopNone	Do not optimize loops in generated code.
StreamLoops	Stream loops.
UnrollLoops	Unroll loops.

Data Types: char | string

MinimizeClockEnables — Omit generation of clock enable logic

false (default) | true

Specify whether to omit generation of clock enable logic.

When false (default), generate clock enable logic.

When true, omit generation of clock enable logic wherever possible.

Data Types: logical

MultiplierPartitioningThreshold — Maximum input bit width for hardware multipliers

none (default) | integer greater than or equal to 2

Specify maximum input bit width for hardware multipliers. If a multiplier input bit width is greater than this threshold, HDL Coder splits the multiplier into smaller multipliers.

To improve your hardware mapping results, set this threshold to the input bit width of the digital signal processor (DSP) or multiplier hardware on your target device.

Data Types: int32

MultiplierSharingMinimumBitwidth — Minimum bit width for shared multipliers

none (default) | integer greater than or equal to 2

Minimum bit width for shared multipliers, specified as a positive integer.

If ShareMultipliers is true and ResourceSharing is greater than 1, share multipliers only if multiplier bit width is greater than or equal to MultiplierSharingMinimumBitwidth.

Data Types: int32

OutputPipeline — Number of output pipeline register stages

0 (default) | integer greater than 0

Specify the number of output pipeline register stages. When DistributedPipelining is enabled, these registers can be distributed through the design.

Data Types: int32

RegisterInputs — Insert pipeline register at each DUT input

false (default) | true

Enable to insert a register at each DUT input. Distributed pipelining does not move these registers.

Data Types: logical

RegisterOutputs — Insert pipeline register at each DUT output

false (default) | true

Enable to insert a register at each DUT output. Distributed pipelining does not move these registers.

Data Types: logical

PreserveDesignDelays — Preserve design delays

false (default) | true

Prevent distributed pipelining from moving design delays or allow distributed pipelining to move design delays, specified as a logical.

Persistent variables and dsp.Delay System objects are design delays.

Data Types: logical

ShareAdders — Share adders

false (default) | true

Specify whether to share adders. If true, share adders when ResourceSharing is greater than 1 and adder bit width is greater than or equal to AdderSharingMinimumBitwidth.

Data Types: logical

ShareMultipliers — Share multipliers

true (default) | false

Specify whether to share multipliers. If true, share multipliers when ResourceSharing is greater than 1 and multiplier bit width is greater than or equal to MultiplierSharingMinimumBitwidth.

Data Types: logical

SimulateGeneratedCode — Simulate generated code

false (default) | true

Specify whether to simulate generated code.

Data Types: logical

SimulationIterationLimit — Simulation iteration limit

-1 (default) | positive integer

Maximum number of simulation iterations during test bench generation. This property affects only test bench generation, not simulation during fixed-point conversion. When the value is -1 (default), no maximum number of simulation iterations is set.

Data Types: int32

SimulationTool — Simulation tool name

'ModelSim' (default) | 'ISIM' | "ModelSim" | "ISIM"

Specify the simulation tool name.

Data Types: char | string

SynthesisTool — Synthesis tool name

'Xilinx ISE' (default) | 'Altera Quartus II' | 'Xilinx Vivado' | 'Cadence Stratus' | "Xilinx ISE" | "Altera Quartus II" | "Xilinx Vivado" | "Cadence Stratus"

Specify the synthesis tool name.

Data Types: char | string

SynthesisToolChipFamily — Synthesis target chip family name

'Virtex4' (default) | 'Family name' | "Family name"

Specify the synthesis target chip family name.

Data Types: char | string

SynthesisToolDeviceName — Synthesis target device name

'xc4vsx35' (default) | 'Device name' | "Device name"

Specify the synthesis target device name.

Data Types: char | string

SynthesisToolPackageName — Synthesis target package name

'ff668' (default) | 'Package name' | "Package name"

Specify the synthesis target package name.

Data Types: char | string

SynthesisToolSpeedValue — Synthesis target speed

'-10' (default) | 'Speed value' | "Speed value"

Specify the synthesis target speed.

Data Types: char | string

SynthesizeGeneratedCode — Synthesize generated code

false (default) | true

Specify whether to synthesize generated code.

Data Types: logical

SystemCTestBenchStimulus — SystemC test bench function name

'HDL Test bench stimulus' (default) | 'Test bench with random input stimulus'

Specify the test bench for SystemC code generation.

Data Types: char | string

TargetFrequency — Target clock frequency

100 (default)

Specify the target frequency, in MHz, of the clock wired to the clock input of the generated HDL design. This frequency is the same as the output clock frequency of the clock module. Adaptive pipelining takes into account the target frequency that you set to improve the frequency of your design.

Data Types: double

TargetLanguage — Target language of the generated code

'VHDL' (default) | 'Verilog' | 'SystemC' | "VHDL" | "Verilog" | "SystemC"

Specify the target language of the generated code.

Data Types: char | string

TestBenchName — Test bench function name

'' (default) | 'Testbench name' | "Testbench name"

Specify the test bench function name. You must specify a test bench.

Data Types: char | string

TimingControllerArch — Timing controller architecture

'default' (default) | 'resettable' | "default" | "resettable"

Specify the timing controller architecture.

TimingControllerArch Value	Description
default	Do not generate a reset for the timing controller.
resettable	Generate a reset for the timing controller.

Data Types: char | string

TimingControllerPostfix — Timing controller postfix

'_tc' (default) | 'Postfix' | "Postfix"

Postfix to append to the design name to form the name of the timing controller.

Data Types: char | string

UseFileIOInTestBench — Use data files for test bench input and output data

true (default) | false

Specify whether to create and use data files for reading and writing test bench input and output data.

Data Types: logical

VHDLLibraryName — Target library name for generated VHDL^® code

'work' (default) | 'Library name' | "Library name"

Specify the target library name for generated VHDL code.

Data Types: char | string

Cosimulation

GenerateCosimTestBench — Generate a cosimulation test bench

false (default) | true

Specify whether to generate a cosimulation test bench.

Data Types: logical

SimulateCosimTestBench — Simulate generated cosimulation test bench

false (default) | true

Specify whether to simulate a generated cosimulation test bench. This option is ignored if GenerateCosimTestBench is false.

Data Types: logical

CosimClockEnableDelay — Time delay before clock enable

0 (default)

Time (in clock cycles) between deassertion of reset and assertion of clock enable.

Data Types: int32

CosimClockHighTime — Time that clock is high

5 (default)

The number of nanoseconds the clock is high.

Data Types: int32

CosimClockLowTime — Time that clock is low

5 (default)

The number of nanoseconds the clock is low.

Data Types: int32

CosimHoldTime — Hold time for input signals and forced reset signals

2 (default)

The hold time for input signals and forced reset signals, specified in nanoseconds.

Data Types: int32

CosimLogOutputs — Log and plot outputs of the reference design function and HDL simulator

false (default) | true

Specify whether to log and plot outputs of the reference design function and HDL simulator.

Data Types: logical

CosimResetLength — Cosimulation reset length

2 (default)

Specify the time (in clock cycles) between assertion and deassertion of reset.

Data Types: int32

CosimRunMode — HDL simulator run mode during simulation

'Batch' (default) | 'GUI' | "Batch" | "GUI"

Specify the HDL simulator run mode during simulation. When in Batch mode, you do not see the HDL simulator UI. The HDL simulator shuts down after simulation.

Data Types: char | string

CosimTool — HDL Simulator

'ModelSim' (default) | 'Incisive' | "ModelSim" | "Incisive"

Specify the HDL simulator for the generated cosim test bench.

Data Types: char | string

FPGA-in-the-loop

GenerateFILTestBench — Generate FIL test bench

false (default) | true

Specify whether to generate a FIL test bench.

Data Types: logical

SimulateFILTestBench — Simulate generated cosimulation test bench

false (default) | true

Specify whether to simulate a generated cosimulation test bench. This option is ignored if GenerateCosimTestBench is false.

Data Types: logical

FILBoardName — FPGA board name

'Choose a board' (default) | 'A board name' | "A board name"

Specify the FPGA board name. You must override the default value and specify a valid board name.

Data Types: char | string

FILBoardIPAddress — IP address of the FPGA board

'192.168.0.2' (default)

Specify the IP address of the FPGA board. You must enter a valid IP address.

Data Types: char | string

FILBoardMACAddress — MAC address of the FPGA board

'00-0A-35-02-21-8A' (default)

Specify the MAC address of the FPGA board. You must enter a valid MAC address.

Data Types: char | string

FILAdditionalFiles — List of additional source files to include

'' (default) | 'Additional source files' | "Additional source files"

Specify a list of additional source files to include. Separate file names by using a semicolon (;).

Data Types: char | string

FILLogOutputs — Log and plot outputs of the reference design function and FPGA

false (default) | true

Specify whether to log and plot outputs of the reference design function and FPGA.

Data Types: logical

Examples

Generate Verilog Code from MATLAB Code

Create a coder.HdlConfig object hdlcfg.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config

Set the test bench name. In this example, the test bench function name is mlhdlc_dti_tb.

hdlcfg.TestBenchName = "mlhdlc_dti_tb";

Set the target language to Verilog^®.

hdlcfg.TargetLanguage = "Verilog";

Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti.

codegen -config hdlcfg mlhdlc_dti

Generate Cosim and FIL Test Benches

Create a coder.FixptConfig object that has default settings and provide a test bench name.

fixptcfg = coder.config("fixpt"); 
fixptcfg.TestBenchName = "mlhdlc_sfir_tb";

Create a coder.HdlConfig object that has default settings and set enable rate.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config
hdlcfg.EnableRate = "DUTBaseRate";

Instruct MATLAB to generate a cosim test bench and a FIL test bench. Specify an FPGA board name.

hdlcfg.GenerateCosimTestBench = true;
hdlcfg.FILBoardName = "Xilinx Virtex-5 XUPV5-LX110T development board";
hdlcfg.GenerateFILTestBench = true;

Perform code generation, Cosim test bench generation, and FIL test bench generation.

codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_sfir

Alternatives

You can also generate HDL code from MATLAB code using the HDL Workflow Advisor. For more information, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.

Version History

Introduced in R2014b