addAXI4StreamInterface

Write data to IP core or read data from IP core using AXI4-Stream interface

Since R2020b

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Syntax

addAXI4StreamInterface(hFPGA)
addAXI4StreamInterface(hFPGA, Name,Value)

Description

addAXI4StreamInterface(hFPGA) adds an AXI4-Stream interface that you can use to control the DUT ports mapped to AXI4-Stream interfaces in the HDL Coder™ generated IP core from MATLAB®.

example

addAXI4StreamInterface(hFPGA, Name,Value) adds an AXI4-Stream interface that you can use to control the DUT ports mapped to AXI4-Stream interfaces in the HDL Coder generated IP core from MATLAB, with one or more properties specified as name-value pair arguments. Enclose each property and value pair in single quotes.

example

Examples

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Add an AXI4-Stream interface to control HDL IP core generated for a Xilinx® target.

Create a target object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function.

addAXI4StreamInterface(hFPGA, ...
    ... % Interface properties
    "InterfaceID", "AXI4-Stream", ...
    "WriteEnable", true, ...
    "ReadEnable", true, ...
    "WriteFrameLength", 1024, ...
    "ReadFrameLength", 1024, ...
    ... % Driver properties
    "WriteDeviceName", "mwipcore0:mm2s0", ...
    "ReadDeviceName", "mwipcore0:s2mm0",...
    "WriteDataWidth", 32, ...
    "ReadDataWidth", 32);

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4-Stream Interfaces.

Add an AXI4-Stream interface for a Xilinx target with only a write channel.

Create a target object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function. Set ReadEnable to false.

addAXI4StreamInterface(hFPGA, ...
    ... % Interface properties
    "InterfaceID", "AXI4-Stream", ...
    "ReadEnable", false, ...
    "WriteFrameLength", 1024, ...
    ... % Driver properties
    "WriteDeviceName", "mwipcore0:mm2s0");

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4-Stream Interfaces.

Input Arguments

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fpga object for the target vendor, specified as an fpga object.

Name-Value Arguments

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Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: addAXI4StreamInterface(hFPGA, "InterfaceID", "AXI4-Stream") creates an AXI4-Stream interface with InterfaceID as AXI4-Stream.

Name of AXI4-Stream interface that you want to map the DUT ports to, specified as a string.

Write channel enable signal, specified as either true or false. By default, WriteEnable is true, and you can write data into the slave channel of the AXI4-Stream interface on the IP core.

Read channel enable signal, specified as either true or false. By default, ReadEnable is true, and you can read data from the master channel of the AXI4-Stream interface on the IP core.

Name and path of the IIO core device that you want to write to, specified as a string. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:mmw2s0.

Name and path of the IIO device that you want to read from. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:s2mm0.

Length of the data vector to write to the streaming device, specified as a scalar. Calculate the effective number of elements written in each streaming operation by dividing the WriteFrameLength argument by the SamplePackingFactor argument.

Length of the data vector that is read from the streaming device, specified as a scalar. Calculate the effective number of elements read in each streaming operation by dividing the ReadFrameLength argument by the SamplePackingFactor argument.

Maximum timeout for the AXI4-Stream write, specified as a scalar.

Maximum timeout for the AXI4-Stream read, specified as a scalar.

Write channel data width, specified as an integer.

Example: 'WriteDataWidth',32 specifies write channel data width of 32 bits.

Read channel data width, specified as an integer.

Example: 'ReadDataWidth',32 specifies read channel data width of 32 bits.

Data processing order, specified as a string. Use this argument only when the input data is in matrix form.

Example: 'FrameProcessingOrder',"RowMajor"

Data Types: char | string

Number of elements per streamed sample, specified as a scalar. To calculate the effective number of elements transferred in each streaming operation, divide the ReadFrameLength or WriteFrameLength parameters by the SamplePackingFactor parameter.

Example: SamplePackingFactor = 4

Strategy to align elements within streamed samples, specified as a string. The default "PowerOf2Aligned", pads each element with zeros to the nearest power of two before packing them together. Alternatively, use "BitAligned" to pack elements directly adjacent to each other without padding. For complex elements, SampleAlignment must be set to "PowerOf2Aligned". Use this parameter only when you set SamplePackingFactor to a value greater than one.

Example: SampleAlignment = "PowerOf2Aligned"

Version History

Introduced in R2020b

See Also

Objects

Functions

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