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Last seen: 6ヶ月前 | 2021 年からアクティブ

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Issue with Implementing System Clock Constraint in FPGA in the Loop (FIL) Toolbox
Make the following changes, and try again. Sum of IR lengths AFTER: 4 User1 Instruction: 100100000010 User2 Instruction: 1001...

8ヶ月前 | 0

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FIL Simulation Failure on Xilinx ZU19EG: "Did not receive version information" Error (MATLAB 2024b + Vivado 2021.2)
The FPGA clock pin could be wrong. Can you share the board manual file?

9ヶ月前 | 0

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Issue with Implementing System Clock Constraint in FPGA in the Loop (FIL) Toolbox
you can save the custom constraints as an .xdc file, and add the xdc file as the source files in FIL Wizard. click 'Add', choos...

9ヶ月前 | 0

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How can I establish hardware-in loop implementation of PYNQ-Z2 on MATLAB using filWizard?
Please try the following changes in the FPGA board wizard: Clock Frequency: 125MHz Clock Pin number: H16 Also connect the Eth...

約1年前 | 0

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Results in FPGA-in-loop is different from Vivado simulation and how to debug
Did you set Reset asserted level to 'Active-low'?

2年弱前 | 0

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Failed to download the third-party software: FTDI JTAG D2XX library
Please refer to this solution. https://www.mathworks.com/matlabcentral/answers/2017321-the-404-error-when-installing-hdl-verifi...

約2年前 | 0

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AXI manager not working with Vivado 2023.1
Hi Dan, Vivado 2023.1 will be supported in R2024a. It's not recommended to use this version for R2023a because it hasn't been t...

2年以上前 | 0

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Issue Connecting to Xilinx FPGA Board for Simulation （Windows ，ZYNQ） Error:Did not receive version information from the hardware.
As mentioned on this help doc. https://www.mathworks.com/help/hdlverifier/ug/fpga-board-editor-reference.html If you are usin...

2年以上前 | 0

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HDL Coder FPGA In The Loop, Error: There is no current hw_target
The message means it failed to program FPGA with JTAG, which should not happen if you are using Ethernet interface. Please be m...

3年弱前 | 0

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Issue Connecting to Xilinx FPGA Board for Simulation
I am unable to find the manual for this board online. I can double check your pin setting if you can direct me to any doc/manual...

3年弱前 | 0

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Issue Connecting to Xilinx FPGA Board for Simulation
Have you installed adept2? https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/InstallDigilentAdept2Runtime.html

3年弱前 | 0

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Is it possible to do co-cimulation for target Nexys A7?
We don't support Neyxs A7 board out-of-the-box, but you can create a custom board for FPGA-in-the-loop simulation. I think JTAG...

約3年前 | 0

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Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.
Can you check if xterm is installed? FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

約3年前 | 0

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Set up HDL verifier
The command line window shows "Expected programming file not generated". You may need to check the project log see why the bit ...

約3年前 | 0

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Bitstream generation problem in HDL coder
At the last step in HDL Workflow Advisor, the FIL project will be synthesized, and then an external shell will pop up to continu...

3年以上前 | 0

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HDL Verifier Max Bit Width Using System Object
Hi David, Do you mean FIL system object? FIL doesn't support sytem verilog HDL. Can you attach your code and elaborate your wor...

約4年前 | 0

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Xilinx ZCU111 OFDM example doesn't load
Can you rerun the hardware setup for the support package? Please follow "Hardware Setup" section as mentioned in https://www.m...

4年以上前 | 1

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Error in example "5G NR Cell Search Using Xilinx RFSoC Device"
Hi, Do you mean you have successfully finished the last 'load' screen of socBuilder, but saw error when you click the 'Monitor ...

5年弱前 | 0