Issue Connecting to Xilinx FPGA Board for Simulation

I was trying to connect to my Xilinx FPGA board using MATLAB to run an FPGA-in-the-loop simulation, and I keep getting an error message. This error occurs in the validation step while using the "FPGA Board Manager" tool. It seems like there is some sort of compatability issue with the FPGA connection, but I'm not sure what.

Here are the screenshots:

Here's the text of the error Message:

To stop the test, press "Ctrl+C" in the MATLAB console window.
Starting FPGA-in-the-Loop test ...
    Generating FPGA programming file ...Passed
    Programming FPGA ...Passed
    Running FIL simulation ...Failed
    Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.

I've tried looking at all the other MATLAB forum posts for this issue, and I didn't see any solutions. I've also tried different values for the JTAG clock frequency, but that also didn't work. :(

Any help would be greatly appreciated!

Version Information: Ubuntu 22.04 LTS, Vivado 2022.2, Matlab R2022b

[Ken]

Hello, I use the development board is also ZYNQ7020, has generated the bit stream file, running matlab, there are the following problems, do you have such a problem? Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.

Answer 1

[YP]

I am unable to find the manual for this board online. I can double check your pin setting if you can direct me to any doc/manual.

I noticed that the reset pin is 'active-low'. Is that correct? If you are not sure about the polarity, can you remove the definition about reset pin as it is optional?

[Max]

I tried running without the reset pin, and I got the same error message. Here are my full settings:

For the pin information, I'm very confident that the clock pins (BA34/BB34) are correct since I compared the FPGA-in-the-loop .rpt file with a previous .rpt file that had been generated from a working vivado project, and the clock pins matched up.

Also, I'm not sure if I'm allowed to share the schematic for my FPGA board (HTG930) publicly.

[YP]

Check the bsdl of this device

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/bsdl-models/ultrascale-plus-series-fpgas.html

First try these fixes:

1. User1 instruction: 000010100100100100
2. JTAG clock frequency: 66

If possible, change to another clock source.

If this is the only clock source, check the generated Vivado project for clock constraints and clock input buffer instantiation, against your working Vivado project, as I don't think DIFF_HSTL_I_12 IO standard is ever tested.

[Max]

I tried experimenting with the new settings, and I was able to get a new error message (which seems better than before):

To stop the test, press "Ctrl+C" in the MATLAB console window. Starting FPGA-in-the-Loop test ... 
    Generating FPGA programming file ...Passed 
    Programming FPGA ...Passed 
    Running FIL simulation ...Failed 
    Error:FIL cosimulation failed: the output does not match the expected result.

Screenshots of my current setting:

I tried a bunch of different combinations for settings, and it seems like the main one that made a difference was setting "User1 instruction" to 000010100100100100.

Also, I tried a couple of other changes that didn't seem to make a difference:

• For JTAG clock frequency I tried a bunch of different speeds. 66 MHz seemed too high and produced the old error ("Did not receive version information"), but 5 MHz, 7.5 MHz, and 15 MHz all produced the same new error.
• Changing User2, User3, User4 instructions to the longer values from the .bdsl file also didn't seem to make a difference.
• For the "FPGA Input Clock" settings I tried using a different clock source and Clock IO standard (LVDS), and that didn't seem to make a difference.

Thanks for helping me make progress!

[YP]

Some questions:

1. Have you successfully run FIL before with other FPGA board using the same host machine? Do you have Windows machine to try?
2. Is the FPGA device the only device in the jtag chain?

One last thing to try:

1. (Very Important) Make a backup copy of <matlabroot>\toolbox\shared\eda\fil\+eda\+internal\+filhdl\@mwfil_xjtagtop\mwfil_xjtagtop.p
2. Replace this file with attached file after unzip.
3. Restart MATLAB, and try again.
4. If it still fail, revert the p file to the original version.

Let me know if it works.

If it doesn't work, we can't help much as we don't have access to the hardware.

I noticed that this board has PCIe. If you want MATLAB to communicate with the board, you can consider PCIe based AXI Manager.

https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/pci-express-axi-manager.html

https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/access-fpga-mem-using-pcie-aximaster.html

[Max]

Hi YP,

Thank you so much, everything worked correctly when I loaded in the new .p file . :-)

Here are the screenshots of the fpga board manager for future reference by other people who might run into the same issue.

Best,

Max

[YP]

Good new.

This fix is will applied to MATLAB R2023b.

[壹 王]

Thank you Very Much ！

Answer 2

[YP]

Have you installed adept2?

https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/InstallDigilentAdept2Runtime.html

[Max]

Yes, I've installed the digilent software and checked that the cable works by programming the FPGA using vivado.

Answer 3

[Lucky]

Hi All,

I am Facing the Same problem Can anyone Help me I have tried the Solution which has been Posted Here,

I am using Basys3 Xilinx FPGA Board and Having the same problem

[YP]

@Lucky This question has been answered.

Please create a new one with more detail or contact Technical Support as your board is different from OP's board.