Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

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Eduardo Flores
Eduardo Flores 2020 年 12 月 27 日
回答済み: YP 2022 年 11 月 21 日
After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?
  1 件のコメント
Cau Tran
Cau Tran 2022 年 8 月 11 日
I also had this problem. Can anyone give me advice for this one?
FIL does not generate the bitstream file.

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回答 (1 件)

YP
YP 2022 年 11 月 21 日
Can you check if xterm is installed?
FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

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