Set up HDL verifier
古いコメントを表示
how can i fix this problem?
PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.
回答 (1 件)
YP
2022 年 11 月 21 日
0 投票
The command line window shows "Expected programming file not generated".
You may need to check the project log see why the bit file gen failed.
カテゴリ
ヘルプ センター および File Exchange で FPGA, ASIC, and SoC Development についてさらに検索
2021 年 1 月 16 日
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!
Translated by 
