hdl coder work flow adviser block compability error

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Fahri Gürbüz
Fahri Gürbüz 2020 年 8 月 18 日
編集済み: Kiran Kintali 2021 年 1 月 25 日
Dear all,
I have a model so as to control a pmsm. when I run the hdl workflow adviser to generate VHDL code, an error which is not clear for me has been occured on the step "check block compability". The error message and related blocks are given as follows;
Simulink BlockWarnings/Errors
Error: Slope and bias scaling 'sfix32_S1p953125en7' is not supported for HDL code generation. Slope must be equal to a power of 2, and bias should always be 0.
I need help about solution of the error.
Thannks in advance.
Regards
Fahri

回答 (4 件)

Kiran Kintali
Kiran Kintali 2021 年 1 月 25 日
編集済み: Kiran Kintali 2021 年 1 月 25 日
Running hdlsetup command on the model targeted for FPGA always helps in terms of data type selection.
web(fullfile(docroot, 'hdlcoder/ref/hdlsetup.html'))
web(fullfile(docroot, 'hdlcoder/ug/check-for-safe-model-parameters.html'))
One of the things this command does is setting ProdHWDeviceType Device vendor to ASIC/FPGA and this greatly helps in coming up with optimal full-precision types for HDL Code generation.

Kiran Kintali
Kiran Kintali 2020 年 8 月 18 日
HDLCoder only supports binary-point scaling. The product currently does not support slope/bias scaling.
You need to choose fixed-point types with a sign bit, fixed wordlength and fraction length.
For ex: A signal with type fixdt(1, 32, 16) as shown on the signal like sfix32_En16 has the following range.
>> a = fi(pi, 1, 32, 16)
a =
3.1416
DataTypeMode: Fixed-point: binary point scaling
Signedness: Signed
WordLength: 32
FractionLength: 16
>> range(a)
ans =
1.0e+04 *
-3.2768 3.2768
DataTypeMode: Fixed-point: binary point scaling
Signedness: Signed
WordLength: 32
FractionLength: 16

Angel de Castro Martín
Angel de Castro Martín 2021 年 1 月 25 日
Hi. Similar problem here. This thread gave me the hint for solving it. I don't know why, the I (integrator) and D (derivative) try to use "strange" data types if let to choose by default (Inherit: inherit via internal rule). In my case, in which I was trying just a PI, I got to compile correctly setting only the "Additional data type" of "Integrator output". The rest can use inherit, but not this one. I also set the type of the input, but not of the global output. I attach a screenshot. I hope this helps future users.

Fahri Gürbüz
Fahri Gürbüz 2020 年 8 月 19 日
Dear Kiran Kintali,
First of all, thanks for your fast answer. I have used all data either single or fixed-point and as you know hdl coder supports both. Thus, I think there is another problem that I could not see. Input signal data type of speed controller is ufix16_En15. I could not see, what is the problem. Maybe, data length exceed the maximum limit. However, input is 16 bits. If you have any idea, I can follow it.
Regards
Fahri
  5 件のコメント
Fahri Gürbüz
Fahri Gürbüz 2020 年 8 月 20 日
Hi Kiran,
The error was occured integrator output of PI controller and I could not make any change on it. I have omitted the PI controller and set it with discrete element and set the data type. The problem is solved.
Thanks for your attention and help @Kiran Kintali @Walter Raberson
Fahri Gürbüz
Fahri Gürbüz 2020 年 12 月 17 日
Hi,
Sorry for late answer. I have passed the problem by setting data types again.
Thanks for advices.
Regards,
Fahri

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