how to generate sine wave for fpga?

67 ビュー (過去 30 日間)
Muhammad Fajri Sachruddin
Muhammad Fajri Sachruddin 2019 年 1 月 11 日
編集済み: Bharath Venkataraman 2021 年 8 月 17 日
I need help for making a sine wave to implement on fpga.
i've read several article and reference about this topic, and still have no idea how to use hdl coder and matlab for this task. I already tried the simplest one which make a LUT in matlab then make the verilog code.
But, I wanna know if there is way to create sine wave with matlab and simulink then convert it using HDL Coder? I didn't really know how to use matlab and simulink. and what i have to do to use hdl coder. if there's a reference that i can read, it would really helpful.
I would really appreciate for any help.
Thanks.
  2 件のコメント
Bharath Venkataraman
Bharath Venkataraman 2021 年 8 月 17 日
I showed how to generate a single frequency sine wave in this post. You can modify the model to change the phase increment to create the appropriate frequency desired.

サインインしてコメントする。

回答 (3 件)

Zeke van Sanchez
Zeke van Sanchez 2019 年 1 月 12 日
If you want a sine wave generator, then one of the most efficient ways to do this would be to instantiate a CORDIC generator. A good example of doing this as part of a signal generator is available here:
Here's the open-source HDL used for the project:
The CORDIC generator used in the project is part of the FPGA manufacturer's free libraries. They're quick to instantiate, easy to setup, and very efficient in terms of logic utilization because they are architected and optimized to each FPGA generation.

Bharath Venkataraman
Bharath Venkataraman 2019 年 1 月 15 日
You can use the self-guided tutorial on HDL Coder to see how to use the tool. The HDL Optimized NCO block in Simulink will allow you to generate a sine wave.

Kiran Kintali
Kiran Kintali 2021 年 7 月 9 日
Attached model generates HDL Code using HDL Coder.
>> makehdl(gcb)
### Generating HDL for 'sine_cust_hdl/WaveGen HDL'.
### Using the config set for model sine_cust_hdl for HDL code generation parameters.
### Running HDL checks on the model 'sine_cust_hdl'.
### Begin compilation of the model 'sine_cust_hdl'...
### Applying HDL optimizations on the model 'sine_cust_hdl'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 43 cycles.
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'sine_cust_hdl'.
### Working on sine_cust_hdl/WaveGen HDL/nfp_mul_single as hdlsrc\sine_cust_hdl\nfp_mul_single.vhd.
### Working on sine_cust_hdl/WaveGen HDL/nfp_sincos_single as hdlsrc\sine_cust_hdl\nfp_sincos_single.vhd.
### Working on sine_cust_hdl/WaveGen HDL as hdlsrc\sine_cust_hdl\WaveGen_HDL.vhd.
### Generating package file hdlsrc\sine_cust_hdl\WaveGen_HDL_pkg.vhd.
### Code Generation for 'sine_cust_hdl' completed.
### Creating HDL Code Generation Check Report WaveGen_HDL_report.html
### HDL check for 'sine_cust_hdl' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
>>

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by