[HDL Coder] How to keep subsystems port names when applying input/output pipelining

Hello,

I am currently developping a control algorithm which will be implemented inside a Xilinx Spartan6 FPGA. I generate the VHDL code using HDL Coder.

In order to optimize the system frequency, I use "input/output pipeline" options for several subsystems.

The problem is that the modified model, from which the code is generated, is composed of the same subsystems, but the in/out ports have different names than they have in my original design.

The names are generic ones (in0, in1,...out0, out1...) whereas I named them with explicit words according to the signals they are connected to.

My question is:

How is it possible to keep the original in/out port names for my subsystems when generating VHDL code from a modified model including input&output pipelines?

MATLAB/Simulink/HDL-Coder version: 2013b

Thanks by advance for your help.

Regards

Grégory SEABRA

[Peyman K. Reghbati]

Hi,

Actually I have the same question. Sometimes I get the right port name, sometimes the generics.

Thanks

--

Peyman

Answer 1

[Kiran Kintali]

Hi, Can you share the model and generated code? Thanks.