Sampling rate in Simulink model and HDL coder

Hi,

I am generating HDL code using HDL coder from Simulink model. Initially my model samples at 75Khz. Further the rate is down sampled to 25KHz. And then the model works at sampling rates of multiples of 25KHz due to upsampling by a factor of 10,8,5 and further a 5 etc. When I generate code for this model using HDL coder I get the basic clock rate as (1/(75e3*totalupsampling factor)) instead of (1/(25e3*totalupsampling factor)).Please suggest a reason for this.Such a clock period is inconveniance when synthesizing the code as it is difficult to generate a high frequency input clock.Please suggest a reason for this.

Krishnakumar

Answer 1

[Bharath Venkataraman]

The base clock period is determined from the rates you put in Simulink. If you model only using the rates that are multiples of 25KHz, you will get the basic clock rate as a multiple of 25KHz.