Code generation option in HDL coder for high clock frequency
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I am working with simulink model whose code is generated by HDL coder. My design has a number of filter stages. The code generated for some filter stages performed as desired in FPGA .But when the design moves to higher clock frequencies HDL coder generated code fails to perform satisfactorily. Please inform me if there is any option to be activated in HDL coder for optimized clock generation in higher frequencies.
回答 (1 件)
Kiran Kintali 2021 年 6 月 22 日
Use critical path estimation feature to estimate the critical path in your model. This workflow in HDL Coder does not involve synthesis.
To get more accurate timing picture with routing delays use Back Annotation feature after synthesis step in workflow advisor.