Main Content

Generate Tests

Generate sets of tests to satisfy model and code coverage and custom testing criteria

Test generation produces sequences of input values for your models to satisfy testing criteria, such as model coverage. Simulink® Design Verifier™ extends existing model coverage information from requirements-based tests. It generates additional sequences of test inputs that meet the coverage objectives not satisfied during requirements-based testing. Use these test inputs to better understand missing requirements and to create a more complete test harness.

Blocks

expand all

Test ConditionConstrain signal values in test cases
Test ObjectiveDefine custom objectives that signals must satisfy in test cases
DetectorDetect true duration on input and construct output true duration based on output type
ExtenderExtend true duration of input
ImpliesSpecify condition that produces a certain response
Within ImpliesVerify response occurs within desired duration
Verification SubsystemSpecify proof or test objectives without impacting simulation results or generated code

Functions

expand all

sldvoptionsCreate design verification options object
sldv.conditionTest condition function for Stateflow charts and MATLAB Function blocks
sldv.testTest objective function for Stateflow charts and MATLAB Function blocks
sldvextractExtract subsystem or subchart contents into new model for analysis
sldvtimerIdentify, change, and display timer optimizations
sldvoptionsCreate design verification options object
sldvrunAnalyze model
sldvlogsignalsLog simulation input port values
sldvgencovAnalyze models to obtain missing model coverage
sldvgenspreadsheetGenerate spreadsheet containing test cases
sldvruntestSimulate model by using input data
sldvruntestoptsGenerate simulation or execution options for sldvruntest or sldvruncgvtest
sldvharnessoptsDefault options for sldvmakeharness
sldvmakefilterGenerate filter file containing justification rules for objectives like Unsatisfiable, Dead Logic, Falsified, Falsified - No Counterexample, and Falsified - Needs Simulation in sldvData file
sldvmakeharnessGenerate harness model
sldvmergeharnessMerge test cases and initializations into one harness model
sldvreportGenerate Simulink Design Verifier report
sldvchecksumReturns checksum of model

Topics

Start Here

Generate Tests for Model Decision Coverage

Generate Tests for Custom Code in a Model

Generate Tests for Analyzable Model Components

Generate Tests to Complete Coverage of Generated Code