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Clock

Generate clock signal for logic systems

  • Library:
  • Simulink Extras / Flip Flops

  • Clock block

Description

The Clock block generates a clock signal for logic systems. The Clock block outputs 1 for the first half of the specified sample period and 0 for the other half of the sample period. You can use the Clock block to control the execution of the D Flip-Flop and J-K Flip-Flop blocks (in the Simulink Extras / Flip Flops library), and other enabled and triggered subsystems.

Ports

Output

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Clock signal, specified as a 1 for the first half of the sample period, and 0 thereafter.

Data Types: double

Parameters

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Specify the sample period. The Clock block outputs 1 for the first half of the sample period. The sample period must be a scalar.

Version History

Introduced before R2006a