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runWorkflow

コシミュレーションワークフローを実行し、必要なアーティファクトを生成する

R2022b 以降

ページ内をすべて折りたたむ

構文

runWorkflow(cosimConfigObj)

runWorkflow(cosimConfigObj,RestartFromStep=1)

説明

例

runWorkflow(cosimConfigObj) は、ワークフローのすべてのステップを実行して、協調シミュレーションブロックまたはSystem object™と、 cosimulationConfigurationオブジェクトで構成されている必要なスクリプトを作成します。

例

runWorkflow(cosimConfigObj,RestartFromStep=1) は、指定されたステップから開始してワークフローステップを実行します。

例

すべて折りたたむ

デフォルトの構成値を使用してワークフローを実行します。

シミュレーター、ワークフロー、トップレベルモデル、および Verilog ファイルを設定し、ワークフローを実行して、自動的に決定された構成値を含む HDL コシミュレーションブロックを生成します。

c = cosimulationConfiguration('Xcelium','Simulink','fir_filt')  
c.HDLFiles = {'./rcosflt_rtl.v','Verilog'};
runWorkflow(c);

前回の協調シミュレーションウィザードの実行に基づいてアーティファクトを生成

'./mygoodrun/cosimWizard_mytop.mat'に保存された以前のワークフローを復元します。

c = cosimulationConfiguration('./mygoodrun/cosimWizard_mytop.mat');
runWorkflow(c);

ワークフローをステップ 1 から再開する

'previousRun.mat'に保存された以前のワークフローを復元します。

前回の実行からワークフローを復元し、 runWorkflowを実行します。

c = cosimulationConfiguration('previousRun.mat');
runWorkflow(c);

-------------------- Step 1------------------
Select the type of cosimulation you want to do. If the HDL simulator executable
you want to use is not on the system path in your environment, you must specify
its location.
-------------------- Step 2------------------
Add all VHDL, Verilog, and/or script files to be used in cosimulation to the 
following table. If the file type cannot be automatically detected or the 
detection result is incorrect, specify the correct file type in the table. 
If possible, we will determine the compilation order automatically using HDL 
simulator provided functionality. Then the HDL files can be added in any order.
Index in position 2 exceeds array bounds. Index must not exceed 1.

Error in CosimWizardPkg.FileSelection/EnterStep

Error in cosimulationConfiguration/l_Step2 (line 809)
                obj.stepH.EnterStep(obj.ddgH)

Error in cosimulationConfiguration/runWorkflow (line 473)
                feval(['l_Step' currStepStr], obj); %wizH, stepH, ddgH, inArgs);

エラーが発生した場合は、HDL ファイルを指定して、手順 1 から実行を再開します。

c.ResetPortRegularExpression = 'rst_p';
runWorkflow(c, 'RestartFromStep', 1);

-------------------- Step 1------------------
Select the type of cosimulation you want to do. If the HDL simulator executable
you want to use is not on the system path in your environment, you must specify
its location.
-------------------- Step 2------------------
Add all VHDL, Verilog, and/or script files to be used in cosimulation to the 
following table. If the file type cannot be automatically detected or the 
detection result is incorrect, specify the correct file type in the table. 
If possible, we will determine the compilation order automatically using HDL 
simulator provided functionality. Then the HDL files can be added in any order.
-------------------- Step 3------------------
HDL Verifier has automatically generated the following HDL compilation commands. 
You can customize these commands with optional parameters as specified in the HDL 
simulator documentation but they are sufficient as shown to compile your HDL code 
for cosimulation. The HDL files will be compiled when you click Next.
Compiling HDL files. Please wait ...
### Compiling HDL design
Reading pref.tcl 
 
# 2021.4 
 
# Create design library 
vlib work 
# ** Warning: (vlib-34) Library already exists at "work". 
# Errors: 0, Warnings: 1 
# Create and open project 
project new . compile_project 
# Loading project compile_project 
project open compile_project 
# Add source files to project 
set SRC1 "." 
# . 
project addfile "$SRC1/rcosflt_rtl.v" 
# Calculate compilation order 
project calculateorder 
# QuestaSim-64 vlog 2021.4 Compiler 2021.10 Oct 13 2021 
# Start time: 12:49:55 on Jul 18,2022 
# vlog -work work -vopt C:/examples/rcosflt_rtl.v  
# -- Compiling module rcosflt_rtl 
#  
# Top level modules: 
# 	rcosflt_rtl 
# End time: 12:49:55 on Jul 18,2022, Elapsed time: 0:00:00 
# Errors: 0, Warnings: 0 
# Compile of rcosflt_rtl.v was successful. 
# All compile dependencies have been resolved. 
set compcmd [project compileall -n] 
# vlog -work work -vopt -stats=none {C:/examples/rcosflt_rtl.v} 
# Close project 
project close 
# reading modelsim.ini 
# Compile all files and report error 
if [catch {eval $compcmd}] { 
    exit -code 1 
} 
# QuestaSim-64 vlog 2021.4 Compiler 2021.10 Oct 13 2021 
# -- Compiling module rcosflt_rtl 
#  
# Top level modules: 
# 	rcosflt_rtl 
#  
# <EOF> 
...done
-------------------- Step 4------------------
Specify the name of the HDL module for cosimulation. The Cosimulation Wizard will 
launch the HDL simulator, load the specified module, and populate the port list 
of that HDL module before the next step. Use "Shared Memory" communication 
method if your firewall policy does not allow  TCP/IP socket communication.
Elaborating and Loading HDL simulation image. Please wait ...
Waiting for HDL Simulator to startup ...
120 seconds to time-out ...
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup ...
119 seconds to time-out ...
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup ...
118 seconds to time-out ...
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup ...
117 seconds to time-out ...
To stop this process, press Ctrl+C in MATLAB console.
Waiting for HDL Simulator to startup ...
116 seconds to time-out ...
To stop this process, press Ctrl+C in MATLAB console.
...done
-------------------- Step 5------------------
Specify all input and output port types. Input signals that are identified a
s 'Clock' and 'Reset' signals will be forced in the HDL simulator through 
Tcl commands. You can specify the timing parameters for forced 'Clock' and 
'Reset' signals in the next step. If you want to drive your HDL clock and 
reset signals with Simulink signals, mark them as 'Input'.
-------------------- Step 6------------------
Set the sample time and data type for each output port. You can specify 
the sample time as -1, which means that it will be inherited via back 
propagation in the Simulink model. Back propagation may fail in certain 
circumstances; click Help for details.
-------------------- Step 7------------------
Set clock and reset parameters here. The time in these tables refers to time 
in the HDL simulator.
Please wait while generating waveforms.
...done
-------------------- Step 8------------------
The diagram below shows the current settings for forced 'Clock' and 'Reset' 
signals. The red line represents the time in the HDL simulation at which 
MATLAB/Simulink will start (i.e. cosimulation will start).

To change the MATLAB/Simulink start time relative to the HDL simulation time, 
enter the new start time below. To avoid a race condition, make sure the start 
time does not coincide with the active edge of any clock signal. You can do 
so by moving the start time or by changing the clock active edge in the 
previous step (click Back).
-------------------- Step 9------------------
When you click Finish, the Cosimulation Wizard performs the following actions:
 - Creates and opens a new Simulink model containing an HDL Cosimulation block 
configured to your specifications.
 - Generates the scripts to compile your HDL code and launch the HDL simulator 
according to the choices you made with this assistant.
 - (If you check the box below) Configures the HDL Cosimulation block to assist 
you in setting the simulation timescale when you cosimulate with the generated 
block for the first time. If you do not check the box below, the timescale is 
set to the default of 1 Simulink second = 1 second in the HDL simulator, or 
you may change it below.
Generating blocks ... Please wait.
...done