Automatic Iterative Optimization

Automatic iterative optimization enables you to optimize your clock frequency without specifying individual optimization options, such as input or output pipelining, distributed pipelining, or loop unrolling. Clock frequency is determined by the critical path of your design. Automatic iterative optimization improves clock frequency by inserting pipeline registers to break and shorten the critical path.

You can use hdlcoder.optimizeDesign to optimize your clock frequency in these ways:

Best clock frequency: Specify the maximum number of iterations that you want HDL Coder™ to perform. HDL Coder iterates the optimization to minimize the critical path in your design.
Target clock frequency: Specify a clock frequency target for your design and the maximum number of iterations you want HDL Coder to perform. HDL Coder iterates the optimization until it meets your target clock frequency or reaches the maximum number of iterations.
HDL Coder can determine that your target clock frequency is not achievable because your target clock period is less than the latency of the largest atomic combinational group of logic in your design.

How Automatic Iterative Optimization Works

You can specify your clock frequency goal, the maximum number of iterations, and the timing strategy for the iterative optimization by using the hdlcoder.OptimizationConfig object properties. Depending on the timing strategy that you choose, synthesis (the default) or critical path estimation, the steps that HDL Coder performs for each iteration vary.

Running the automatic iterative optimization with synthesis can take a long time, depending on the complexity of your design. For example, when running the hdl.optimizeDesign function that has synthesis as the timing strategy, synthesis can occupy nearly 94% of the run time of this function. To help mitigate the runtime and still use synthesis, the hdlcoder.optimizeDesign function can regenerate code from a previous run or resume from an interrupted run.

To help mitigate the runtime most effectively, you can choose critical path estimation as your timing strategy. Critical path estimation provides an estimated critical path rather than the actual critical path determined by synthesis. When using critical path estimation, automatic iterative optimization avoids model generation and HDL code generation to help increase the speed of every iteration. Critical path estimation as the timing strategy is most effective for placement of delays and reducing the critical path when you generate a timing database for your target device by first using the genhdltdb function. For an example that runs the hdlcoder.optimizeDesign function using both strategies, see Use Critical Path Estimation for Faster Optimization.

If you choose critical path estimation as your timing strategy, the automatic iterative optimization performs these steps:

Analyzes the logic in your design.
Estimates the critical path, and obtains timing analysis data by using a timing database. For more information, see Critical Path Estimation Without Running Synthesis.
Inserts pipeline registers to break the critical path.
Balances delays.
Saves iteration data in a new folder.

If you choose synthesis as your timing strategy, the automatic iterative optimization performs these steps:

Analyzes the logic in your design.
Generates code.
Uses the synthesis tool to analyze the generated code and obtains post-map timing analysis data.
Back-annotates the design by using the timing analysis data.
Inserts pipeline registers to break the critical path.
Balances delays.
Saves iteration data in a new folder.

When HDL Coder has met your clock frequency goal or it has reached the maximum number of iterations, it saves the generated code and iteration data in a new folder and generates a report that describes the final critical path.

Automatic Iterative Optimization Output

When HDL Coder exits the optimization loop, it saves the results of the final iteration in a folder, hdlsrc/your_model_name/hdlexpl/Final-timestamp.

The final iteration folder contains:

The generated HDL code, in the hdlsrc/your_model_name folder.
A data file, cpGuidance.mat, that you can use with your original model to regenerate code without rerunning the iterative optimization.
The optimization report, summary.html.

Automatic Iterative Optimization Report

HDL Coder generates a report for the final optimization iteration and saves it in the final iteration folder, hdlsrc/your_model_name/hdlexpl/Final-timestamp.

The final optimization report, summary.html, contains:

Summary Section containing:
- Final critical path latency.
- Critical path latency and elapsed time for each iteration.
Diagnostic Section containing:
- Reason for stopping at the final iteration.
- Model or block settings that can reduce the accuracy of the critical path analysis.
  If your model has these settings, remove them where possible, and rerun the hdlcoder.optimizeDesign function. Some optimizations, such as distributed pipelining and constrained output pipeline, change the placement of pipeline registers after the coder analyzes the critical path.
- Critical path description, which shows signals and components in the original model and generated model that are part of the critical path.
  You might see a message that a signal or component on the critical path cannot be traced back to the original model. HDL Coder might not be able to map its internal representation of your design back to the original design. Each optimization iteration changes the internal representation. The final representation can have a structure that is different from your original design.

Automatic Iterative Optimization Synthesis Tool and Hardware

If you are using synthesis as the timing strategy, your synthesis tool must be Xilinx^® ISE or Xilinx Vivado^®. Your target device must be a Xilinx FPGA.

Limitations of Automatic Iterative Optimization

In the current release, automatic iterative optimization does not support Altera^® hardware if you are using synthesis as the timing strategy.
Automatic iterative optimization is available from the command line only.
When the timing strategy is set to synthesis, HDL Coder uses post-map timing information, which the synthesis tool generates before performing place and route. Post-map timing information is less accurate than timing information that the synthesis tool generates after place and route, but is faster to obtain.
When the timing strategy is set to critical path estimation, HDL Coder uses a timing database to estimate the critical path. Critical path estimation yields a less accurate critical path result than synthesis does, but is the fastest option by a substantial amount (about 10x faster depending on your design) for iterative optimization.
When using critical path estimation as the timing strategy, if there are blocks in the model that are not supported by critical path estimation, the results might be less optimal than using synthesis as the timing strategy. The blocks in the model that are not supported by critical path estimation appear as a message in the HDL Code Generation Check Report and the Resource Utilization Report, and as a link to a script to highlight the blocks in the MATLAB^® Command Window.
You cannot compare the iterative optimization timing value for the critical path when using synthesis as the timing strategy to the result when using critical path estimation as the timing strategy. To compare the results, run synthesis on the final design after running hdlcoder.optimizeDesign with critical path estimation as the timing strategy.